Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Skew-tolerant high-speed (STHS) domino logic

Abstract: This paper presents skew-tolerant high-speed domino logic. Skew-tolerant high-speed domino logic resolves the floating dynamic node problem of high-speed domino logic and alleviates the strict clock timing requirement. Simulation results show that skew-tolerant high-speed domino logic is more robust to noise and timing variation than high-speed domino logic, while achieving better performance.

C-CREST Technique for Combinational Logic SET Testing

Abstract: SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the combinational circuit for radiation effects self-test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty.

Interactive teaching of elementary digital logic design with WinLogiLab

Abstract: This paper presents an interactive computerized teaching suite developed for the design of combinatorial and sequential logic circuits. This suite fills a perceived gap in the currently available computer-based teaching software, with the purpose of providing alternative-mode subject delivery. The authors were, therefore, prompted to develop a Microsoft-Windows tutorial suite, WinLogiLab, comprising a set of interactive tutorials that show the link between Boolean algebra and digital combinatorial and sequential circuits. The combinatorial tutorials follow the initial design steps: from Boolean algebra, to truth tables, to minimization techniques, to production of the combinatorial circuit in a seamless way. Similarly, the sequential tutorials can design simple finite-state counters and can model more complex finite-state automata.

Stochastic Digital Circuits for Probabilistic Inference

Abstract: We introduce combinational stochastic logic, an abstraction that generalizes deterministic digital circuit design (based on Boolean logic gates) to the probabilistic setting. We show how this logic can be combined with techniques from contemporary digital design to generate stateless and stateful circuits for exact and approximate sampling from a range of probability distributions. We focus on Markov chain Monte Carlo algorithms for Markov random fields, using massively parallel circuits. We implement these circuits on commodity reconfigurable logic and estimate the resulting performance in time, space and price. Using our approach, these simple and general algorithms could be affordably run for thousands of iterations on models with hundreds of thousands of variables in real time.

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Abstract: A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with the goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72% reduction in performance variation at the expense of average 20% increase in design area.