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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Journal ArticleDOI
TL;DR: A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed that allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS), the high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI.
Abstract: A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware. >

40 citations

Book ChapterDOI
01 Jan 2011
TL;DR: It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs.
Abstract: The paper presents logic synthesis method targeted at FPGA architectures with specialized embedded memory blocks (EMBs). Existing methods do not ensure effective utilization of the possibilities provided by such modules. The problem of efficient mapping of combinational and sequential parts of design can be solved using decomposition algorithms. The main question of this paper is the application of decomposition based methods for efficient utilization of modern FPGAs. It will be shown that functional decomposition method allows for very flexible synthesis of the designed system onto heterogeneous structures of modern FPGAs composed of logic cells and EMBs. Finally we present results of the experiments, which evidently show, that the application of functional decomposition algorithms in the implementation of typical signal and information processing systems greatly influences the performance of resultant digital circuits.

40 citations

Journal ArticleDOI
TL;DR: In this paper, a digital circuit using polymer thin-film transistors on polyester substrate is presented, which consists of 171 transistors and converts a parallel word of four bits into a serial bit sequence by use of gates and flip-flops with level shifters.
Abstract: A digital circuit using polymer thin-film transistors on polyester substrate is presented. The circuit consists of 171 transistors and converts a parallel word of four bits into a serial bit sequence by use of gates and flip-flops with level shifters. The integrated clock generator runs at oscillation frequencies of approximately 200 Hz with supply voltages of -25 V/+12 V. The polymer poly(3,3''-dihexyl-2,2':5',2''-terthiophene) (PDHTT) is used as semiconducting material. Measurement results for the circuit demonstrate that PDHTT can be used for digital polymer circuits.

40 citations

Proceedings ArticleDOI
K. A. Tamura1
01 Jun 1989
TL;DR: A method is presented that determines the areas, within the gate-level circuit, that contain the functional errors and is shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.
Abstract: In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistencies that may exist between the functional-level description and its gate-level implementation. In this paper we present a method that determines the areas, within the gate-level circuit, that contain the functional errors. The indicated areas are shown to have sufficient resolution to allow the designer to quickly find the cause of the inconsistency and, therefore, reduce the time required for debugging.

40 citations

Patent
05 Jul 1994
TL;DR: In this paper, an interpolation-decimation filter is incorporated into the beamformer at a most advantageous place that allows the final beamforming to be simple and performed at a relatively low data rate and allows the higher rate signal processing to be confined to circuitry which may advantageously be on a single type of integrated circuit.
Abstract: In accordance with the principles of the present invention, advantage is taken by the inventors of the fact that the speed of operation of the digital hardware in a digital beamformer can be reduced by providing, for example, multiple phases of the data signals and then processing the multi-phase data in N parallel summing paths An interpolation-decimation filter receives the multi-phase data from the N parallel summing paths and provides at its output a signal having a reduced data rate (1/N) In accordance with this technique, the speed of operation of the individual digital circuits for forming the required beamforming delays is not increased as compared to conventional post-beamforming interpolation schemes, so that hereby the effective data rate is increased by a factor N and results in a decrease of the delay quantization error by a factor N In accordance with the principles of the invention, the interpolation-decimation filter is incorporated into the beamformer at a most advantageous place That is, it is incorporated into the beamformer processing after partial beamforming of a group of receive channels and before formation of the final beam This approach allows the final beamforming to be simple and performed at a relatively low data rate and allows the higher rate signal processing to be confined to circuitry which may advantageously be on a single type of integrated circuit which is repetitively used in the beamformer Further increase in the effective speed of operation is produced by providing timing circuitry that allows parallel processing of signals from a plurality of scanning beam lines

40 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250