Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Logic synthesis for programmable gate arrays

Abstract: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures. >

Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm

Abstract: A new way of diagnosing ICs that fail logic tests is described. It can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.

Chemical Wave Logic Gates

Abstract: Logic gates based on chemical wave propagation in geometrically constrained excitable media are demonstrated in a Belousov−Zhabotinsky membrane system. The catalyst of the reaction is printed in specific predetermined patterns with geometries designed to provide various logic operations. Computational studies of the serial coupling of elements to form multicomponent gates and general chemical wave circuitry are presented.

Improved logic synthesis algorithms for table look up architectures

Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches. >

Gate-length biasing for digital circuit optimization

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.