Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

The essence of logic circuits

Abstract: Introduction boolean algebra applied to logic circuits designing combinational logic circuits combinational logic circuits in regular forms symmetric and iterative circuits sequential logic circuits software tools. Appendices.

Automatic analysis of hybrid systems

Abstract: Hybrid systems are real-time systems that react to both discrete and continuous activities (such as analog signals, time, temperature, and speed). Typical examples of hybrid systems are embedded systems, timing-based communication protocols, and digital circuits at the transistor level. Due to the rapid development of microprocessor technology, hybrid systems directly control much of what we depend on in our daily lives. Consequently, the formal specification and verification of hybrid systems has become an active area of research. This dissertation presents the first general framework for the formal specification and verification of hybrid systems, as well as the first hybrid-system analysis tool--H scYT scECH. The framework consists of a graphical finite-state-machine-like language for modeling hybrid systems, a temporal logic for modeling the requirements of the hybrid systems, and a computer procedure that verifies modeled hybrid systems against modeled requirements. The tool H scYT scECH is the implementation of the framework using C++ and M scATHEMATICA. More specifically, our hybrid-system modeling language, Hybrid Automata, is an extension of timed automata (AD94) with discrete and general continuous variables whose dynamics are governed by differential equations. Our requirement modeling language, I scCTL, is a branching-time temporal logic, and is an extension of T scCTL (ACD93) with stop-watch variables. Our verification procedure is a symbolic model-checking procedure that verifies linear hybrid automata against I scCTL formulas, and is an extension of the symbolic model-checking procedure for real-time systems in (HNSY94). To make H scYT scECH more efficient and effective, we designed and implemented model-checking strategies and abstract operators that can expedite the verification process. To enable H scYT scECH to verify nonlinear hybrid automata, we also introduce two translations from nonlinear hybrid automata to linear hybrid automata that can be fed into H scYT scECH for automatic analysis. We have applied H scYT scECH to analyze more than 30 hybrid-system benchmarks. In this dissertation, we show the application of H scYT scECH to three nontrivial hybrid systems taken from the literature.

Acoustic logic gates and Boolean operation based on self-collimating acoustic beams

Abstract: The reveal of self-collimation effect in two-dimensional (2D) photonic or acoustic crystals has opened up possibilities for signal manipulation. In this paper, we have proposed acoustic logic gates based on the linear interference of self-collimated beams in 2D sonic crystals (SCs) with line-defects. The line defects on the diagonal of the 2D square SCs are actually functioning as a 3 dB splitter. By adjusting the phase difference between two input signals, the basic Boolean logic functions such as XOR, OR, AND, and NOT are achieved both theoretically and experimentally. Due to the non-diffracting property of self-collimation beams, more complex Boolean logic and algorithms such as NAND, NOR, and XNOR can be realized by cascading the basic logic gates. The achievement of acoustic logic gates and Boolean operation provides a promising approach for acoustic signal computing and manipulations.

Digital circuit test generator

Abstract: Automatic test pattern generator for generating test patterns that are capable of detecting faults in a digital combinational circuit comprises a first forward network capable of emulating the digital combinational circuit; a second forward network capable of emulating the digital combinational circuit in the presence of any one target fault from a specified set of faults, and receiving a set of control signals for selecting the target fault; a first backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the first backward network generating one fault activation objective corresponding to the selected target fault, and receiving first signal values computed in the first forward network for propagating the fault activation objective towards a primary output; a second backward network having one primary input for every primary output of the digital combinational circuit and one primary output for every primary input of the digital combinational circuit, the second backward network receiving second signal values computed in the second forward network for propagating the fault activation objective towards a primary output, both the first and second backward networks independently generating and propagating fault-effect propagation objectives towards one or more of its respective primary outputs; a first control device for generating the set of control signals corresponding to a target fault, and selecting the target fault one at a time from the specified set of target faults; means for merging one or more objectives propagated to the primary outputs of the first and second backward network; comparator device for comparing the first and second sets of primary output signals from each the first and second forward network in response to primary input signals, and determining whether at least one pair of corresponding primary outputs have different binary values and providing an output therefor; and, second control device for receiving the merged objectives from the backward network and the comparator output, and determining therefrom primary input values of the first and second forward network for detecting the target fault in the combinational digital circuit.

Testing digital circuits

Abstract: To test a digital data storage circuit which includes two latch elements (5, 10) each formed by two complementary transistor inverter circuits (S1 S2, S3 S4) connected in a positive feedback arrangement and in which the output current capability of the second inverter circuit is restricted to enable the latch element to change state in response to input signals applied to it, a transistor (T3) is blocked (6) and the first latch element (5) is connected in a two elements per bit shift register configuration with the second latch element (10) by series connected transistors (T4, T5) controlled by antiphase square waves (T3T, H1T). During normal operation asynchronous SET and CLEAR signals are used to control three transistors (T1, T2, T6) whereby to be able to apply (via T3) one of two voltage levels to the first latch (5), one of the shift register transistors (T4) being closed. Each latch (5, 10) may be as shown in Fig 2, the transistors being of differing size, as illustrated. … …