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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Patent
16 Jul 1990
TL;DR: In this article, a transmit/receive module including digitally controlled analog circuits is described, and a preferred process to provide digital and analog microwave circuits on a common semiconductor substrate is described.
Abstract: A transmit/receive module including digitally controlled analog circuits is described. The digital circuits use a logic family adapted for use with analog monolithic integrated circuits. The disclosure also describes a preferred process to provide digital and analog microwave circuits on a common semiconductor substrate.

38 citations

Patent
Luke A. Johnson1
17 Jun 1999
TL;DR: In this article, the authors present a method of adjusting a common mode output level of a first differential amplifier that is connected to a first digital circuit, in response to variation in a trip point level of the second digital circuit.
Abstract: An embodiment of the invention is directed to a method of automatically adjusting a common mode output level of a first differential amplifier that is connected to a first digital circuit, in response to variation in a trip point level of a second digital circuit. The second digital circuit includes a replicate of the first digital circuit to generate a trip point level that is equivalent to a trip point level of the first digital circuit. The invention may yield a single-ended digital signal whose duty cycle accurately tracks that of an input differential signal pair in a manner that is substantially independent of fabrication process skew.

38 citations

Journal ArticleDOI
TL;DR: A new design approach oriented to the implementation of binary comparators in QCA is proposed, and new formulations of basic logic equations required to perform the comparison function are proposed.
Abstract: Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.

38 citations

Proceedings ArticleDOI
19 Jul 1999
TL;DR: This paper presents an approach based on the use of genetic programming to synthesize logic functions, using the 1-control line multiplexer as the only design unit, defining any logic function through the replication of this single unit.
Abstract: This paper presents an approach based on the use of genetic programming to synthesize logic functions. The proposed approach uses the 1-control line multiplexer as the only design unit, defining any logic function (defined by a truth table) through the replication of this single unit. Our fitness function first explores the search space trying to find a feasible design and then concentrates on the minimization of such (fully feasible) circuit. The proposed approach is illustrated using several sample Boolean functions.

38 citations

Journal ArticleDOI
TL;DR: Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns.
Abstract: Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns. OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 /spl mu/W.

38 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250