Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Functional modeling of RSFQ circuits using Verilog HDL

Abstract: Circuit level simulation is too slow to be used for verification of function and timing of large RSFQ circuits. The alternative, known from semiconductor digital circuit design, is simulating at the logic (gate) instead of the circuit (transistor or junction) level. Using a hardware description language (HDL) such as Verilog, it is possible to write functional model of each of the RSFQ basic gates. A large RSFQ circuit composed of hundreds gates and thousands Josephson junctions can then be simulated using standard semiconductor industry CAD tools. We have developed a library of Verilog models for over 15 basic RSFQ gates. We describe in detail our model for the DRO RSFQ cell. We show how this model can be generalized for other more complex cells. Our library has been verified by employing it in the design of timing for three large RSFQ circuits.

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Abstract: The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.

MOS folded source-coupled logic

Abstract: In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by a CMOS source-coupled current-steering differential logic topology. In the preferred embodiment, gain and level shifting functions are merged, and connections to the power bus are made through constant current sources.

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

Abstract: A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

Performance-driven mapping for CPLD architectures

Abstract: We present a performance-driven programmable logic array mapping algorithm (PLAmap) for complex programmable logic device architectures consisting of a large number of PLA-style logic cells. The primary objective of the algorithm is to minimize the depth of the mapped circuit. We also develop several techniques for area reduction, including threshold control of PLA fanouts and product terms, slack-time relaxation, and PLA packing. We compare PLAmap with a previous algorithm TEMPLA (Anderson and Brown 1998) and a commercial tool Altera Multiple Array MatriX (MAX) + PLUS II (Altera Corporation 2000) using Microelectronics Center of North Carolina (MCNC) benchmark circuits. With a relatively small area overhead, PLAmap reduces circuit depth by 50% compared to TEMPLA and reduces circuit delay by 48% compared to MAX + PLUS II v9.6.