Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

NBTI-aware synthesis of digital circuits

Abstract: Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the signal probability of each of its inputs, is developed. Accordingly, a technology mapping technique that incorporates the NBTI stress and recovery effects, in order to ensure optimal performance of the circuit, during its entire lifetime, is presented. Our technique, demonstrated over 65 nm benchmarks shows an average of 10 % area recovery, and 12 % power savings, as against a pessimistic method that assumes constant stress on all PMOS transistors in the design.

High-frequency equivalent circuit of GaAs FETs for large-signal applications

Abstract: The application of GaAs field effect transistors in digital circuits requires a valid description by an equivalent circuit at all possible gate and drain bias voltages for all frequencies from DC up to the gigahertz range. An equivalent circuit is presented which takes into account the gate current of positively biased transistors as well as the symmetrical nature of the devices at low drain voltages. A fast method of determining the elements of the equivalent circuit at all bias points without frequency limitations is presented. Direct computation from analytical expressions, without iteration, allows this parameter extraction procedure to be used for real-time on-wafer parameter extraction. Large-signal calculations are possible by inserting the voltage dependences evaluation for the elements into suitable simulation programs, such as SPICE. >

Models and algorithms for bounds on leakage in CMOS circuits

Abstract: Subthreshold leakage current in deep submicron MOS transistors is becoming a significant contributor to power dissipation in CMOS circuits as threshold voltages and channel lengths are reduced. Consequently, estimation of leakage current and identification of minimum and maximum leakage conditions are becoming important, especially in low power applications. In this paper we outline methods for estimating leakage at the circuit level and then propose heuristic and exact algorithms to accomplish the same task for random combinational logic. In most cases the heuristic is found to obtain bounds on leakage that are close and often identical to bounds determined by a complete branch and bound search. Methods are also demonstrated to show how estimation accuracy can be traded off against execution time. The proposed algorithms have potential application in power management applications or quiescent current (I/sub D/DQ) testing if one wished to control leakage by application of appropriate input vectors. For a variety of benchmark circuits, leakage was found to vary by as much as a factor of six over the space of possible input vectors.

Boolean Analysis of MOS Circuits

Abstract: The switch-level model represents a digital metal-oxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network states. This analysis supports the same class of networks as the switch-level simulator MOSSIM II and provides the same functionality, including the handling of bidirectional effects and indeterminate (X) logic values. In the worst case, the analysis of an n-node network can yield a set of formulas containing a total of O(n /sup 3/) operations. However, all but a limited set of dense, pass-transistor networks give formulas with O(n) total operations. The analysis can serve as the basis of efficient programs for a variety of logic design tasks, including logic simulation (on both conventional and special-purpose computers), fault simulation, test generation, and symbolic verification.

Digital PWM control: application in voltage regulation modules

Abstract: Conventionally, controllers for DC/DC converters have relied on analog circuit techniques for implementation. While analog based systems have proven successful, several reasons make digital control attractive. Digital control allows for the implementation of more functional control schemes. Digital circuits are potentially less susceptible to noise and parameter variations. With the explosion of cheap computing power, and availability of advanced integrated circuit design and synthesis tools, a digital controller design can be ported to new integrated circuit technology generations with little additional effort. Current trends in microprocessor designs lead toward decreasing supply voltages and increasing current demands. Future microprocessors are projected to require between 30-60 Amps of static current and impose di/dt requirements on the power supply in the order of 5 A/ns. In this paper, we focus on the design of a digital controller for an interleaved DC/DC buck converter to supply power for microprocessor loads. Digital logic makes the generation of identical, but delayed, gate drive signals for the various phases of the interleaved converter simple.