Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process

Abstract: Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays

Abstract: This paper presents a method based on stochastic logic to analyse fault trees. This method supports both static and dynamic gates, and can be applied to any type of fault trees. In this paper, static and dynamic gates would be translated into stochastic logic templates, and a hardware implementation for each gate would be achieved. Based on these hardware templates, it is possible to implement the whole logic on a Field-Programmable Gate Array (FPGA). Utilizing the stochastic logic for implementing a given fault tree on FPGA, the analysis would outperform the following parameters compared to traditional methods: 1) Speed-up, 2) Simplicity, 3) Reliability, and 4) Accuracy. Experimental results illustrate that using stochastic logic for modeling fault trees results in fast convergence of Monte Carlo simulation. Moreover, on average, our FPGA approach takes 50% of the time required by previous emulation approaches. Simplicity is an additional advantage of the proposed approach, achieved because of simplicity behind stochastic logic. Also, the stochastic logic is more reliable compared to traditional logic because any faults like SEUs in stochastic logic have less impact on the whole results compared to traditional arithmetic logic. To evaluate the proposed technique, the analysis is performed on several standard benchmarks composed of static and dynamic gates. The results obtained using this approach agree with those obtained from an analytical approach, which proves that the method is an accurate tool for system reliability modeling.

IBDDs: an efficient functional representation for digital circuits

Abstract: A central issue in the solution of many computer aided design problems is finding a concise representation for circuit designs and their functional specifications. Ordered binary decision diagrams (OBDDs) have recently emerged as a popular representation for various CAD applications such as design verification, synthesis, testing, modeling and simulation. Unfortunately, there is no efficient OBDD representation for many circuits, even in some cases for circuits which perform such apparently simple functions as multiplication. The authors present a new BDD representation scheme, called indexed BDDs (IBDDs), and show that it allows polynomial representations of functions which provably require exponential space using OBDDs. The key idea in IBDDs is to allow multiple occurrences of the input variables, subject to ordering constraints. The authors give an algorithm for verifying the equivalence of two IBDDs and a heuristic for constructing IBDDs for arbitrary combinational circuits. >

Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance

Abstract: Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous EDS designs while lowering clock energy and removing datapath metastability. Error-recovery circuits replay failing instructions at lower clock frequency to guarantee correct functionality. Relative to conventional circuits, silicon measurements indicate that resilient circuits enable either 25 to 32% throughput gain at equal VCC or at least 17% VCC reduction at equal throughput, resulting in 31 to 37% total power reduction.

Quality assurance and upgrade of analog characteristics by fast mismatch analysis option in network analysis environment

Abstract: In contrast to digital circuits, the fabrication tolerance of electrical characteristics of analog integrated circuits depends highly on the local device matching accuracy. Especially for scaled structures down to the submicrometer range, the local statistical device parameter mismatching increases rapidly. As in network analysis programs (i.e., SPICE), statistical mismatch effects are not represented within the implemented device modeling; consequently no analysis options are available to compute their influence on electrical circuit characteristics in production