Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks

Abstract: To enable essential deep learning computation on energy-constrained hardware platforms, including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC designs have presented customized dataflow and enhanced parallelism. However, in conventional digital designs, the biggest bottleneck for energy-efficient deep neural networks (DNNs) has reportedly been the data access and movement. To eliminate the storage access bottleneck, new SRAM macros that support in-memory computing have been recently demonstrated. Several in-SRAM computing works have used the mix of analog and digital circuits to perform XNOR-and-ACcumulate (XAC) operation without row-by-row memory access and can map a subset of DNNs with binary weights and binary activations. In the single array level, large improvement in energy efficiency (e.g., two orders of magnitude improvement) has been reported in computing XAC over digital-only hardware performing the same operation. In this article, by integrating many instances of such in-memory computing SRAM macros with an ensemble of peripheral digital circuits, we architect a new DNN accelerator, titled Vesti . This new accelerator is designed to support configurable multibit activations and large-scale DNNs seamlessly while substantially improving the chip-level energy-efficiency with favorable accuracy tradeoff compared to conventional digital ASIC. Vesti also employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the row-by-row write latencies of in-memory computing SRAMs. The Vesti accelerator is fully designed and laid out in 65-nm CMOS, demonstrating ultralow energy consumption of $ for CIFAR-10 classification at 1.0-V supply.

Layout-dependent fault analysis and test synthesis for CMOS circuits

Abstract: An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models. >

Graphene nanoribbon based negative resistance device for ultra-low voltage digital logic applications

Abstract: Negative resistance devices offer opportunities in design of compact and fast analog and digital circuits. However, their implementation in logic applications has been limited due to their small ON current to OFF current ratios (peak to valley ratio). In this paper, a design for a 2-port negative resistance device based on arm-chair graphene nanoribbon is presented. The proposed structure takes advantage of electrostatic doping, and offers high ON current (∼700 μA/μm) as well as ON current to OFF current ratio of more than 105. The effects of several design parameters such as doping profile, gate workfunction, bandgap, and hetero-interface characteristics are investigated to improve the performance of the proposed devices. The proposed device offers high flexibility in terms of the design and optimization, and is suitable for digital logic applications. A complementary logic is developed based on the proposed device, which can be operated down to 200 mV of supply voltage. The complementary logic is used in design of an ultra-compact bi-stable switching static memory cell. Due to its compactness and high drive current, the proposed memory cell can outperform the conventional static random access memory cells in terms of switching speed and power consumption.

CRAFTED LOGIC Towards Hand-Crafting a Computer

Abstract: This paper introduces the piece Crafted Logic, an interactive installation realized as part of a larger research into creating electronic components from scratch. The piece consists of fundamental logic gates that are created by various textile-crafting techniques. Each gate is composed of handcrafted relays that are controlled electromagnetically, and is capable of performing a different logical operation. In replicating the basis of digital electronics in novel forms and through unconventional materials, our intention is to imagine alternatives to existing realities of computational technologies. Crafted Logic is a speculative artifact and process as means to reflect on the creation of digital systems that surround us, as well as on how this shapes our interaction with them.

Recent progress of submicron CMOS using 6H-SiC for smart power applications

Abstract: Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated.