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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


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Journal ArticleDOI
TL;DR: A QCA architecture of a new single-layer butterfly switching network (BSN) of quantum-dot cellular automata with considerable enhancement in terms of cell count, device area, and latency, and thereby outperform all reported prior designs.
Abstract: Quantum-dot cellular automata (QCA) is a rapidly growing nanotechnology very well suited for designing ultra-dense, low-power, and high-performance digital circuits. In parallel computing, the multistage interconnection network (MIN) provides maximum bandwidth to the components and minimum latency access to the memory modules. Much research has been conducted on CMOS-based MINs for parallel computing. However, the QCA-based switching network is still underexplored. This article proposes a QCA architecture of a new single-layer butterfly switching network (BSN). To achieve this, we design an efficient 2 × 2 switching element (SE), using a modified majority ( $\mathcal{M}{_{[x,y]}}$ ) gate that is fully utilized (i.e., no fixed logic like “0” and “1” at the inputs). The use of a fully utilized majority gate over a partially utilized majority (PUM) one makes the proposed SE more cost-efficient and versatile, and therefore it is used as the building block for designing the switching network. In addition, we deploy the SE to realize 4 × 4 and 8 × 8 BSNs. We also show how the design can be extended for an N × N BSN. All the proposed circuits have been modeled and verified by QCADesigner. QCAPro is used for estimating the average switching and leakage energy dissipation of the proposed circuits. The results show considerable enhancement in terms of cell count, device area, and latency, and thereby outperform all reported prior designs.

34 citations

Journal ArticleDOI
TL;DR: In this paper, small voltage variations, like those that can be found across an integrated circuit, are shown to affect the digital single event transient response significantly and for technologies with supply voltages near 1 V, these potential variations may result in unexpected vulnerability.
Abstract: Heavy ion-induced single events transients (SETs) in advanced digital circuits are becoming a significant reliability issue for space-based systems. In this work, two experiments are performed on devices designed to look specifically at digital single event transients. Small voltage variations, like those that can be found across an integrated circuit, are shown to affect the digital single event transient response significantly. For technologies with supply voltages near 1 V, these potential variations may result in unexpected vulnerability.

34 citations

Journal ArticleDOI
01 Feb 1986
TL;DR: A new structure of adaptive transversal filters with a large number of taps is described, based on the use of the distributed-arithmetic technique without any multiplier in the realisation of the filter function.
Abstract: A new structure of adaptive transversal filters with a large number of taps is described. It is based on the use of the distributed-arithmetic technique without any multiplier in the realisation of the filter function. In this structure, the N filter taps are divided into M blocks, each with R taps. These M blocks operate simultaneously and thus achieve a high-speed signal processing capability. This type of adaptive filter can easily be implemented by using microprocessor or transistor-transistor logic integrated circuits. A simplified hardware prototype module suitable for 8- and 16-point transversal adaptive filters, using microprocessor and simple peripheral interface circuitry, is presented. Results from this prototype demonstrate the basic feasibility of this structure for implementing digital adaptive filters with a large number of taps.

34 citations

Journal ArticleDOI
TL;DR: In this article, a novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed, where each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits.
Abstract: A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).

34 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250