Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Programmable sequential logic circuit devices

Abstract: The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.

Slope propagation in static timing analysis

Abstract: Static timing analysis has traditionally used the PERT method for identifying the critical path of a digital circuit Due to the influence of the slope of a signal at a particular node on the subsequent path delay, an earlier signal with a signal slope greater than the slope of the later signal may result in a greater delay Therefore, the traditional method for timing analysis may identify the incorrect critical path and report an optimistic delay for the circuit We show that the circuit delay calculated using the traditional method is a discontinuous function with respect to transistor and gate sizes, posing a severe problem for circuit optimization methods We propose a new timing analysis algorithm which resolves both these issues The proposed algorithm selectively propagates multiple signals through each timing edge in cases where there exists ambiguity regarding which arriving signal represents the critical path The algorithm for propagating the corresponding required times is also presented We prove that the proposed algorithm identifies a circuit's true critical path, where the traditional timing analysis method may not We also show that under this method circuit delay and node slack are continuous functions with respect to a circuit's transistor and gate sizes In addition, we present a heuristic method which reduces the number of signals to be propagated at the expense of a slight loss in accuracy Finally, we show how the proposed algorithm was efficiently implemented in an industrial static timing analysis and optimization tool, and present results for a number of industrial circuits Our results show that the traditional timing analysis method underestimates the circuit delay by as much as 38%, while that the proposed method efficiently finds the correct circuit delay with only a slight increase in run time

An ECG-on-Chip for Wearable Cardiac Monitoring Devices

Abstract: This paper describes a highly integrated, low power chip solution for ECG signal processing in wearable devices. The chip contains an instrumentation amplifier with programmable gain, a band-pass filter, a 12-bit SAR ADC, a novel QRS detector, 8K on-chip SRAM, and relevant control circuitry and CPU interfaces. The analog front end circuits accurately senses and digitizes the raw ECG signal, which is then filtered to extract the QRS. The sampling frequency used is 256 Hz. ECG samples are buffered locally on an asynchronous FIFO and is read out using a faster clock, as and when it is required by the host CPU via an SPI interface. The chip was designed and implemented in 0.35um standard CMOS process. The analog core operates at 1V while the digital circuits and SRAM operate at 3.3V. The chip total core area is 5.74 mm^2 and consumes 9.6uW. Small size and low power consumption make this design suitable for usage in wearable heart monitoring devices.

Dynamic Idd test circuit for mixed signal ICs

Abstract: Built-in test circuitry is proposed that uses the dynamic supply current consumption of a mixed signal circuit under test for a unified fault detection method. Simulation waveform are reported to illustrate the performance of the proposed circuitry.

Scanning apparatus for a matrix display panel

Abstract: A scanning apparatus for a matrix display panel having a plurality of picture elements at the intersections of X- and Y-line conductors. The scanning apparatus has an X-line driving circuit, Y-line driving circuit, a video signal generator, a timing signal generator, a width control signal generator, a second switching circuit and an analog-to-digital converter. The Y-line driving circuit has a plurality of sets of first memory circuits, a set of second memory circuits, a set of first switching circuits, and a set of brightness control circuits. The scanning apparatus is capable of reproducing moving images having many steps of gray scale from coded video signals having relatively few bits by digital circuits and is also capable of finely controlling the brightness by the efficient use of a horizontal sweep retrace period of the video signals with simplified circuits.