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Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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08 Dec 2003
TL;DR: Four previously published piecewise linear and one piecewise second-order approximation of the sigmoid function are compared with SIG-sigmoid, a purely combinational approximation and it is concluded that the best performance is achieved by SIG-Sigmoid.
Abstract: Special attention must be paid to an efficient approximation of the sigmoid function in implementing FPGA-based reprogrammable hardware-based artificial neural networks. Four previously published piecewise linear and one piecewise second-order approximation of the sigmoid function are compared with SIG-sigmoid, a purely combinational approximation. The approximations are compared in terms of speed, required area resources and accuracy measured by average and maximum error. It is concluded that the best performance is achieved by SIG-sigmoid.
166 citations
Book•
01 Oct 2001
TL;DR: This chapter discusses SOI CMOS Devices--Part I, PD SOI-Technology SPICE Models, and Fundamentals of SOICMOS Circuits.
Abstract: Preface. Acknowlegments. Introduction. SOI CMOS Devices--Part I. SOI CMOS Devices--Part II. Fundamentals of SOI CMOS Circuits. SOI CMOS Digital Circuits. SOI CMOS Analog Circuits. PD SOI-Technology SPICE Models. Index.
163 citations
TL;DR: In this paper, the authors proposed a Digital Electronic and Analog Photonic (DEAP) architecture for convolutional neural networks (CNNs) that has potential to be 2.8 to 14 times faster while using almost 25% less energy than current state-of-the-art graphical processing units (GPUs).
Abstract: Convolutional Neural Networks (CNNs) are powerful and highly ubiquitous tools for extracting features from large datasets for applications such as computer vision and natural language processing. However, a convolution is a computationally expensive operation in digital electronics. In contrast, neuromorphic photonic systems, which have experienced a recent surge of interest over the last few years, propose higher bandwidth and energy efficiencies for neural network training and inference. Neuromorphic photonics exploits the advantages of optical electronics, including the ease of analog processing, and busing multiple signals on a single waveguide at the speed of light. Here, we propose a Digital Electronic and Analog Photonic (DEAP) CNN hardware architecture that has potential to be 2.8 to 14 times faster while using almost 25% less energy than current state-of-the-art graphical processing units (GPUs).
162 citations
TL;DR: An implementation of an invertible gate to bring out the key role of a three-terminal building block to enable the construction of correlated p-bit networks and establishes this result with examples including a 4-bit multiplier which in inverted mode functions as a factorizer.
Abstract: Digital electronics are based on deterministic units called bits that can have one of two values, 0 and 1. New theoretical work suggests that circuits built out of probabilistic units that fluctuate randomly in value between 0 and 1 can be used to perform multiple functions: A multiplier, for example, can also function as a factorizer.
160 citations
TL;DR: The first experimental demonstration of recently proposed single flux quantum logic, eSFQ, is reported, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic.
Abstract: We report the first experimental demonstration of recently proposed energy efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ∼0.8 aJ/bit operation. Two types of demonstration eSFQ circuit, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA cm−2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
159 citations