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Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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TL;DR: This paper reviews several of the current-mode CMOS multiple-valued logic (MVL) circuits that have been studied over the past decade and their performance described.
Abstract: Current-mode CMOS circuits are receiving increasing attention. Current-mode CMOS multiple-valued logic circuits are interesting and may have applications in digital signal processing and computing. In this paper we review several of the current-mode CMOS multiple-valued logic (MVL) circuits that we have studied over the past decade. These circuits include a simple current threshold comparator, current-mode MVL encoders and decoders, current-mode quaternary threshold logic full adders (QFAs), current-mode MVL latches, current-mode latched QFA circuits, and current-mode analog-to-quaternary converter circuits. Each of these circuits is presented and its performance described. >
147 citations
TL;DR: In this article, the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs).
Abstract: This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs). After introducing the classification and the terminology used in this paper, we firstly present the basis of the different transport models used in device-level simulation (drift-diffusion, hydrodynamic, Monte-Carlo and some approximated and exact quantum-mechanical based approaches). We also focus on the main emerging physical phenomena affecting ultra-short MOSFETs (quantum effects, tunneling current, ballistic operation) and the methods envisaged for taking them into account at device simulation level. Several examples of device simulation are given at the end of this first part, including recent results on fully-depleted SOI and multiple-gate devices. In the second part, we briefly survey the different circuit-level modeling approaches (circuit-level simulation, Mixed-Mode, 3-D simulation of portions of circuits) of single-event effects in integrated circuits. The SEU in advanced SRAM and SEE mechanisms in logic circuits are reminded. The production and propagation of digital single-event transients (DSETs) in sequential and combinational logic, as well as the soft error rate trends with scaling are particularly addressed. Recent bibliographical examples of simulation in SRAMs and logic circuits are presented and discussed to illustrate these topics at circuit-level.
146 citations
TL;DR: Digitally assisted analog circuits can exploit digital circuits' high density and low energy per computation to enable a new generation of interface electronics based on minimal-precision, low-complexity analog building blocks.
Abstract: Today's interfaces between digital and "real world" analog signals rely mainly on complex analog circuit components that strictly limit achievable power efficiency and throughput. Digitally assisted analog circuits can exploit digital circuits' high density and low energy per computation to enable a new generation of interface electronics based on minimal-precision, low-complexity analog building blocks
145 citations
TL;DR: The throughput of synchronous and asynchronous interconnect is compared and a discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay.
Abstract: A unified framework and terminology is presented for synchronization design in digital systems, borrowing techniques and terminologies from digital system and digital communication design disciplines. The throughput of synchronous and asynchronous interconnect is compared, emphasizing how it is affected by interconnect delay. A discussion is presented of opportunities to apply principles long used in digital communications to the design of digital systems, with the goal of reducing the dependence on interconnect delay. >
145 citations
Book•
21 Oct 2005
TL;DR: The bipolar Current-mode inverter is used as a guide for the design of CPE/NPE circuits because it simplifies the overall design of the system and makes it easier to understand the role of the amplifier in the system.
Abstract: Acknowledgment. Preface. 1. Devices Modeling for Digital Circuits. 1.1. PN JUNCTION. 1.1.1. Reverse Bias Condition. 1.1.2. Foward Bias Condition. 1.2. BIPOLAR-JUNCTION TRANSISTORS. 1.2.1 Basic Operation. 1.2.2. Early Effect or Base Width Modulation. 1.2.3. Charge Effects in the Bipolar Transistor. 1.2.4. Small Signal Model.1.3. MOS TRANSISTORS. 1.3.1. Basic Operation. 1.3.2. Triode or Linear Region. 1.3.3. Saturation or Active Region. 1.3.4. Body Effect. 1.3.5. p-channel Transistors. 1.3.6. Charge Effects in Saturation Region. 1.3.7 Charge Effects in Triode Region. 1.3.8. Charge Effects in Cutoff Region. 1.3.9. Small Signal Model. 1.3.10. Second Order Effects in MOSFET Modeling. 2. Current-Mode Digital Circuits. 2.1. The bipolar Current-mode inverter: basic principles. 2.2. The bipolar Current-mode inverter: Input-Output CharacteristicS and noise margin. 2.2.1. Differential input/output. 2.2.2. Single-ended input/output..2.2.3. Considerations on the non zero input current. 2.2.4. Remarks and comparison of differential/single-ended gates. 2.3. The buffered bipolar Current-mode (ECL) inverter. 2.4. The MOS Current-mode inverter. 2.4.1. Static modeling of the PMOS active load. 2.4.2. Input-output characteristics. 2.4.3. Evaluation of the noise margin. 2.4.4. Validation of the static model. . 2.4.5. The buffered MOS Current-Mode inverter and remarks. 2.5. Fundamental Current-mode logic gates. 2.5.1 Principle of operation of Current-Mode gates: the series gating concept. 2.5.2. Some examples of Current-Mode series gates. 2.5.3. Supply voltage limitations in bipolar Current-Mode gates. 2.5.4. MOS Current-Mode series gates and supply voltage limitations. 2.6. Typical applications of Current-mode circuits. 2.6.1. Radio Frequency applications. 2.6.2. Optic-fiber communications. 2.6.3. High-resolution mixed-signal ICs. 3. Methodologies for complex Current-mode logic gates. 3.1. BASIC CONCEPTS ON THE DESIGN OF A SERIESGATE. 3.1.1. Evaluation of function F(X1...Xn) implemented by a given topology. 3.1.2. Series-gate implementation of an assigned function F(X1...Xn). 3.1.3. Limitations of the general series-gate design approach. 3.2. A GRAPHICAL REDUCTION METHOD. 3.2.1. Basic concepts on the graphical approach in [CJ89]. 3.2.2. A design example. 3.3. an analytical formulation of the design strategy IN [CJ89]. 3.3.1. Analytical interpretation of CPE/NPE. 3.3.2. Analytical simplification through CPE/NPE: an example. 3.3.3. Circuit implementation of the simplified function after CPE-NPE. 3.4. A VEM-BASED REDUCTION METHOD. 3.5. INPUT ORDERING VERSUS DESIGN GOAL. 4. Modeling of Bipolar Current-mode gates. 4.1. Introduction to Modeling methodologies. 4.2. AN EFFICIENT APPROACH FOR CML GATES. 4.3. Simple modeling of THE CML inverter. 4.3.1. Accuracy of the CML simple model. 4.4. Accurate modeling of THE CML inverter. 4.4.1. Accuracy of the CML accurate model. 4.5. Simple AND ACCURATE modeling of THE ECL inverter. 4.5.1. Validation and improvement of the ECL model.4.6. SIMPLE modeling of bipolar CML MUX/XOR gates. 4.6.1. Validation of the MUX/XOR model. 4.6.2.Extension to the MUX/XOR when upper transistors switch. 4.7. ACCURATE modeling of bipolar CML MUX/XOR gates AND EXTENSION TO ECL GATES. 4.8. EVALUATION OF CML/ecl GATES INPUT CAPACITANCE. 4.9. bipolar Current-mode D Latch. 5. Optimized Design of Bipolar Current-mode gates. 5.1. Introduction to optimized methodology in cml gates. 5.2. OPTIMIZED DESIGN OF THE CML INVERTER. 5.2.1. Design with minimum transistor area. 5.2.2. Design with non-minimum transistor area. 5.2.3. Design examples. 5.3. OPTIMIZED DESIGN OF THE ECL INVERTER. 5.4. COMPARISON BETWEEN THE CML AND THE ECL INVERTER. 5.5. OPTIMIZED DESIGN OF BIPOLAR CURRENT-MODE MUX/XOR AND D LATCH. 5.5.1. Design of MUX/XOR CML gates with minimum transistor area. 5.5.2. Design of MUX/XOR CML gates with
144 citations