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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Patent
El Ayat Khaled A1
13 Feb 1991
TL;DR: In this article, a user-programmable integrated circuit includes an analog component containing user-configurable analog circuit modules, a digital component consisting of user configurable digital circuit modules and an interface portion containing userconfigurable interface circuits for conversion of signals from analog to digital and from digital to analog.
Abstract: A user-programmable integrated circuit includes an analog portion containing user-configurable analog circuit modules, a digital portion containing user-configurable digital circuit modules, an interface portion containing user-configurable interface circuits for conversion of signals from analog to digital form and from digital to analog form, and a user-configurable interconnection and input/output architecture.

112 citations

Journal ArticleDOI
TL;DR: In this article, the authors present the test results of superconductor-insulator-ferromagnet-superconductor (SIFS) MJJs showing their applicability for superconducting spintronic memory and digital circuits.

112 citations

Book
01 Jan 1966
TL;DR: In this article, the authors present AC-circuit analysis and analog and digital measurements for direct current, alternating current, and diode circuits, including transistors, operational amplifiers, and oscillators.
Abstract: Direct Current Circuits. Alternating Currents. Diode Circuits. Semiconductor Devices. AC-Circuit Analysis. Transistor Amplifiers. Operational Amplifiers. Oscillators. Digital Electronics. Analog and Digital Measurements. Microprocessors. Microprocessor Circuits. Appendices. Index.

111 citations

Proceedings ArticleDOI
13 Jul 2000
TL;DR: This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs, and it is shown that in general the principles of evolving digital circuits are scalable.
Abstract: A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit. This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.

111 citations

Journal ArticleDOI
TL;DR: The reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits, is presented, applicable to dynamic logic gates as well.
Abstract: The subject of this paper is the reduction of transistor-level models of CMOS logic gates to equivalent inverters, for the purpose of computing the supply current in digital circuits. No restrictions are applied to either the number of switching inputs or the transition times and relative delays of the input voltages. The relative positions of the switching inputs are also accounted for in the case of series-connected MOSFET's. When combined with our previously reported CMOS inverter model, the peak current is obtained in a time approximately three orders faster than HSPICE with the level-3 MOSFET model. The corresponding accuracy is around 12%. If the current waveform is required, the speed improvement is about an order less. Since the inverter model also yields the delay at no extra cost, the timing of the current waveforms can be done automatically, without recourse to a timing simulator. Although the emphasis here is on CMOS static gates, the method is applicable to dynamic logic gates as well. >

110 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250