Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

BooleDozer: logic synthesis for ASICs

Abstract: Logic synthesis is the process of automatically generating optimized logic-level representation from a high-level description. With the rapid advances in integrated circuit technology and the resultant growth in design complexity, designers increasingly rely on logic synthesis to shorten the design time while achieving performance objectives. This paper describes the IBM logic synthesis system BooleDozer™, including its organization, main algorithms, and how it fits into the design process. The BooleDozer logic synthesis system has been widely used within IBM to successfully synthesize processor and ASIC designs.

A unified single-phase clocking scheme for VLSI systems

Abstract: Two of the main consequences of advances in VLSI technologies are increased cost of design and wiring. In CMOS synchronous systems, this cost is partly due to tedious synchronization of different clock phases and routing of these clock signals. Here, a single-phase clocking scheme that makes the design very compact and simple is described. It is shown that this scheme is general, simple, and safe. It provides a structure that can contain all components of a digital VLSI system, including static, dynamic, and precharged logic as well as memories and PLAs. Clock and data signals are presented in a clean way that makes VLSI circuits and systems well suited for design compilation. >

Speed and area tradeoffs in cluster-based FPGA architectures

Abstract: One way to reduce the delay and area of field-programmable gate arrays (FPGAs) is to employ logic-cluster-based architectures, where a logic cluster is a group of logic elements connected with high-speed local interconnections. In this paper, we empirically evaluate FPGA architectures with logic clusters ranging in size from 1 to 20, and show that compared to architectures with size 1 clusters, architectures with size 8 clusters have 23% less delay (30% faster clock speed) and require 14% less area. We also show that FPGA architectures with large cluster sizes can significantly reduce design compile time-an increasingly important concern as the logic capacity of FPGA's rises. For example, an architecture that uses size 20 clusters requires seven times less compile time than an architecture with size 1 clusters.

Fault modeling for the testing of mixed integrated circuits

Abstract: The goal of the research described in this paper is to introduce a fault-modeling technique for simulating defective analog components in Mixed Analog/Digital Integrated Circuits. The proposed fault- modeling strategy has been implemented to develop analog fault models representing the effect of spot defects in CMOS circuits. Results from an initial study of opamps are summarized and detailed results from onc example are included as an illustration of the fault- modeling process. 1 Introduction Application of analog components within large digital systems - a typical configuration in modern mixed analog/digital IC's - generates many new challenges in both design and testing areas (l), (2), (3), (4). EspccialIy difficult to solve are testing problems due to the observability limitations caused by the nature of the boundary between the digital and analog components of mixed IC's. Although there are many mixcd IC testing problems, this paper focuses on only one of them - a strategy of fault simulation. More specifically, this paper introduces a fault- modeling methodology which could be applied to capture the malfunctioning of analog components in mixed IC's. The goal of the reported research is to develop fault models that enable efficient simulation of the entire mixed IC by using a technique that is as close as possible to traditional digital circuit simulation techniques. Hence, this paper concentrates solely on the fault- modeling technique. It is organized in the following way. In Section 2, the general fault-modeling methodology developed for analog components of mixed IC's is introduced. In Section 3, an implementation of this methodology for CMOS technology is described in morc detail. Finally, in Section 4, an attempt to generalize obtained results is made in order to determine the practicality of the proposed fault-modeling methodology. This section also gives a list of problems to be solved in the subsequent research dealing with testing of mixcd analog/digital integrated circuits.