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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Journal ArticleDOI
Shuang Gao1, Fei Zeng1, Minjuan Wang1, Guangyue Wang1, Cheng Song1, Feng Pan1 
TL;DR: Two methods for the implementation of complete Boolean logic functions in a single CRS cell are reported, one based on the intrinsic switchable diode of a peculiar CRScell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state and another based directly on the complementary switching behaviour itself of any single C RS cell.
Abstract: The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage.

84 citations

Book ChapterDOI
01 Jan 2013
TL;DR: Variations in process, supply voltage and temperature (PVT) have always been an issue in Integrated Circuit (IC) Design and IC designers have to quantify these uncertainties and account for them adequately.
Abstract: Variations in process, supply voltage and temperature (PVT) have always been an issue in Integrated Circuit (IC) Design. In digital circuits, PVT fluctuations affect the switching speed of the transistors and thus the timing of the logic. To guarantee fault-free operation for a specified clock frequency, IC designers have to quantify these uncertainties and account for them adequately. This is typically done by guard-banding, i.e. adding sufficient voltage safety margin to ensure proper working even under worst-case condition.

84 citations

Journal ArticleDOI
01 Oct 1971
TL;DR: In this paper, the operation and applications of charge-coupled shift registers for digital signals are described and simple signal-regeneration stages are analyzed and their operation is demonstrated by two-phase and three-phase CCSs made by p-MOS process.
Abstract: This paper describes the operation and the applications of charge- coupled shift registers for digital signals. Simple signal-regeneration stages for digital charge-coupled shift registers are analyzed and their operation is demonstrated by charge-coupled circuits made by a p-MOS process. A charge-transfer efficiency of about 99.6 percent per electrode at a clock frequency of 1 MHz was obtained in the operation of three-phase 8-bit shift registers made by the p-MOS process. Silicon-gate construction is proposed for achieving high- performance high-density structures and also two-phase charge-coupled devices.

84 citations

Proceedings ArticleDOI
06 Nov 1994
TL;DR: This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration.
Abstract: This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.

84 citations

Book
14 Mar 2014
TL;DR: This paper presents methods for optimization of finite state machines for FPGA-based circuits and systems and designs of digital circuits and system on the basis of FPGAs.
Abstract: Part I Design of digital circuits and systems on the basis of FPGA.- Part II Methods for optimization of finite state machines for FPGA-based circuits and systems.

84 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250