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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Journal ArticleDOI
TL;DR: Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB and the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.
Abstract: Oversampling and digital filtering have been used to design a per-channel voiceband codec with resolution that exceeds the typical transmission system requirement by more than 15 dB. This extended dynamic range will allow for the use of digital processing in the management of signal levels and system characteristics in many telecommunication applications. Digital filtering contained in the codec provides rejection of out-of-band inputs and smoothing of the analog output that is sufficient to eliminate the need for analog filtering in most telephone applications. Some analog filtering may be required only to maintain the expanded dynamic range in cases where there is a danger of large amounts of out-of-band energy on the analog input impairing the dynamic range of the modulator. The encoder portion of the oversampled codec comprises an interpolating modulator that samples at 256 kHz followed by digital filtering that produces a 16-bit PCM code at a sample rate of 8 kHz. In the decoder, digital processing is used to raise the sampling rate to 1 MHz prior to demodulation in a 17-level interpolating demodulator. The circuits in the codec are designed to be suitable for large-scale integration. Component matching tolerances required in the analog circuits are of the order of only ± 1 percent, While the digital circuits can be implemented with fewer than 5000 gates with delays on the order of 0.1 μs. In this paper the response of the codec is described mathematically and the results are confirmed by measurements of experimental breadboard models.

79 citations

Journal ArticleDOI
28 Jun 2004
TL;DR: A mixed-signal programmable chip for high-speed vision applications that can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format in less than 1 ms, together with the possibility of executing sequences of user-definable instructions makes the chip a true general-purpose sensory/processing device.
Abstract: This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

79 citations

Book
30 Aug 1999
TL;DR: Fault-finding: inspecting for faults faults in analogue circuits faults in digital circuits.
Abstract: Essential facts: useful terms and equations useful circuits circuit calculations. Devices: diodes transistors sensors and transducers. Circuits: amplifiers oscillators operational amplifiers more operational amplifier applications power amplifiers power control devices logic circuits combinatorial logic sequential logic display devices conversion devices. Communication systems: communication transmission media noise signals radio communication. Systems: control systems microprocessor systems microprocessors memory programming software. Fault-finding: inspecting for faults faults in analogue circuits faults in digital circuits.

79 citations

Journal ArticleDOI
TL;DR: A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown, which has reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises.

79 citations

Patent
Jawahar Jain1
28 Oct 1998
TL;DR: In this article, a system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions is presented.
Abstract: A system and method for representing digital circuits and systems in multiple partitions of Boolean space, and for performing digital circuit or system validation using the multiple partitions. Decision diagrams are built for the digital circuit or system and pseudo-variables are introduced at decomposition points to reduce diagram size. Pseudo-variables remaining after decomposition are composed and partitioned to represent the digital circuit or system as multiple partitions of Boolean space. Each partition is built in a scheduled order, and is manipulable separately from other partitions.

79 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250