Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former

Abstract: A digital computer of relatively simple and efficient structural organization which is capable not only of conventional arithmetic operations according to a program but also of (i) performing chained Boolean logic processing on any selected bit of any of various selected words held in memory, (ii) using the logic processing result by storing it at any selected bit location in any of various selected words held in memory, and/or (iii) causing different, predetermined instructions within a program to have their execution dependent upon the results of previously performed single bit logic processing. The logic processing is carried out in response to specially coded instruction words which may be randomly interspersed between conventional arithmetic instruction steps within an overall program. Existing registers and apparatus components necessary for conventional arithmetic operations are utilized in large measure to carry out the routing of signals to and from the logic processor, and very little added hardware is required to create the logic processing, storing, and dependent conditioning.

On path selection in combinational logic circuits

Abstract: The authors have developed a polynomial-time algorithm to find a minimum cardinality path set that can be used to verify the correct operation of a digital circuit. Although they have assumed that the circuit under consideration is a combinational logic circuit constructed from AND, OR, NAND, NOR, and NOT gates, circuits containing other types of gates can be accommodated by using an appropriate circuit model for such gates. The algorithms are also directly applicable to sequential circuits that use the so-called scan design, since in such circuits it is only necessary to test the combinational circuit embedded between latches. >

20 ${\hbox{kA/cm}}^{2}$ Process Development for Superconducting Integrated Circuits With 80 GHz Clock Frequency

Abstract: Results of the development of an advanced fabrication process for superconductor integrated circuits (ICs) with 20 kA/cm2 Nb/AlOx/Nb Josephson junctions is presented. The process has 4 niobium superconducting layers, one MoNx resistor layer with 4.0 Ohm per square sheet resistance for the junction shunting and circuit biasing, and employs circular Josephson junctions with the minimum diameter of 1 mum; total 11 photolithography levels. The goal of this process development is the demonstration of the feasibility of 80 GHz clock speeds in superconducting ICs for digital signal processing (DSP) and high performance computing. Basic components of rapid single flux quantum (RSFQ) logic such as DC/SFQ, SFQ/DC converters, Josephson transmission lines (JTLs), and simple digital circuits such as T-flip-flops and 4-bit digital counters have been fabricated and tested. The T-flip-flops were shown to operate up to 400 GHz with the widest margin of operation of plusmn13% at 325 GHz. Digital testing results on the 4-bit counters as well as the junctions, resistors, and other process parameters are also presented. Prospects for yet higher speeds and very large scale integration are discussed.

1.2 V CMOS switched-capacitor circuits

Abstract: In battery-powered portable systems, low-voltage CMOS integrated circuits are essential for low power consumption. While integrating analog and digital circuits on the same chip, it is preferred that both analog and digital circuits share the same voltage supplies. However, a low supply voltage forces severe constraints on the design of analog circuits and the conventional CMOS transmission gates may no longer be adequate or even functional as analog switches if the signal swing of the switch control is kept between the nominal supply voltages. Design techniques for 1.2 V CMOS switched-capacitor (SC) circuits are described. MOS transistors with low-threshold voltages are not required. The signal paths are fully differential to maximize noise immunity against disturbances from supplies and substrate, critical when a large number of digital circuits are on the same chip. The analog switches are implemented with nMOS transistors. An on-chip high-voltage generator is used to generate the high-voltage required to turn on the nMOS switches. The circuits use a 0.8 /spl mu/m n-well double-poly double-metal CMOS technology. The threshold voltages are 0.7 V for the nMOSTs, and -0.8V for the pMOSTs.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

Abstract: We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.