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Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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TL;DR: In this article, a combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized, and a simple analytical model which accurately predicts the transient response of the BiCMOS gate is described.
Abstract: A combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized. A simple analytical model which accurately predicts the transient response of the BiCMOS gate is described. At moderate and large loads, saturation of the bipolar transistors due to collector resistance can dominate the transient response. Device scaling issues are discussed for minimizing gate delay at various loading conditions. >
77 citations
17 Jun 1990
TL;DR: A wafer-scale-integration neural network has been fabricated and evaluated and the 16-city traveling salesman problem could be solved in less than 0.1 s by using this network, which was 10 times faster than a Hitachi supercomputer.
Abstract: A wafer-scale-integration (WSI) neural network has been fabricated and evaluated. 576 digital neurons are integrated and interconnected with each other on a 5-in silicon wafer by using 0.8-mm CMOS. Neural functions are faithfully mapped to binary digital circuits. The 9-bit output and the 8-bit synapse weight of each neuron are variable. A time-sharing digital bus architecture overcomes the disadvantage of digital neuron circuits. This WSI neural network can be connected with a host computer and used for a wide range of artificial neural networks. The 16-city traveling salesman problem could be solved in less than 0.1 s by using this network. This speed was 10 times faster than a Hitachi supercomputer. Larger artificial neural networks can be realized by simply connecting WSIs
77 citations
TL;DR: In this paper, the main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths, and it is found that the main cause of jitter strongly depends on the power supply configuration of the PLL.
Abstract: When integrating analog and digital circuits onto a mixed-mode chip, power supply noise coupling is a major limitation on the performance of the analog circuitry. Several techniques exist for reducing the noise coupling, of which one of the cheapest is separating the power supply distribution networks for the analog and digital circuits. Noise coupling from a digital noise-generating circuit through the power supply/substrate into an analog phase-locked loop (PLL) is analyzed for three different power supply schemes. The main mechanisms for noise coupling are identified by comparing different PLLs and varying their bandwidths. It is found that the main cause of jitter strongly depends on the power supply configuration of the PLL. Measurements were done on mixed-mode designs in a standard 0.25-/spl mu/m digital CMOS process with a low-resistivity substrate. The same circuits were also implemented with triple-well processing for comparisons.
77 citations
14 Apr 1998
TL;DR: This work proposes the first technique that leverages the unique characteristics of FPGAs to protect commercial investment in intellectual property through fingerprinting, and imposes additional constraints on the back-end CAD tools for circuit place and route.
Abstract: Advanced CAD tools and high-density VLSI technologies have combined to create a new market for reusable digital designs. The economic viability of the new core-based design paradigm is pending on the development of techniques for intellectual property protection. A design watermark is a permanent identification code that is difficult to detect and remove, is an integral part of the design, and has only nominal impact on performances and cost of design. Field Programmable Gate Arrays (FPGAs) present a particularly interesting set of problems and opportunities, because of their flexibility. We propose the first technique that leverages the unique characteristics of FPGAs to protect commercial investment in intellectual property through fingerprinting. A hidden encrypted message is embedded into the physical layout of a digital circuit when it is mapped into the FPGA. This message uniquely identifies both the circuit origin and original circuit recipient, yet is difficult to detect and or remove. While this approach imposes additional constraints on the back-end CAD tools for circuit place and route, experiments involving a number of industrial-strength designs indicate that the performance impact is minimal.
76 citations
TL;DR: The first experimental demonstration of single flux quantum logic, eSFQ, was reported in this article. But the authors did not report the performance metrics of the eSFLQ circuits.
Abstract: We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
76 citations