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Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, a new structure of the pulse generator based on two long underdamped Josephson junctions is proposed, which is characterized by the reduced power consumption and reduced output noise.
Abstract: Devices of three types: magnetic pulse generators, read-out circuits, and digital circuits controlling them are needed to support scalable operation of quantum logic based on the Josephson junction qubits. The most natural framework for implementation of such a classical interface to quantum circuits is provided by the RSFQ technology . In this work, we argue, however, that specific qubit requirements can not be satisfied with the conventional RSFQ approach and describe the necessary modifications. We suggest a new structure of the pulse generator based on two long underdamped Josephson junctions which is characterized by the reduced power consumption and reduced output noise. We also show how to trade off power consumption and speed of the digital control circuits by using Josephson junctions with similar values of the shunt resistors but very different critical currents. Finally, we suggest a new read-out circuit which enables dynamic compensation of the backaction down to the level approaching fundamental quantum-mechanical limit.

76 citations

Patent
31 Jan 1991
TL;DR: In this article, a separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator, which allows control of the quantization noise transfer function profile independently of the forward signal transfer function.
Abstract: A separate filter circuit is inserted between the D/A converter and the summing junction in the feedback path of a conventional sigma delta modulator. This additional filter allows control of the quantization noise transfer function profile independently of the forward signal transfer function. By proper tailoring of the transfer functions a third or higher order modulator can be constructed without instability developing. The modulator can also be constructed as a completely digital circuit and used as a noise shaping circuit in a digital digital-to-analog converter.

76 citations

Journal ArticleDOI
TL;DR: Gate-level pipelining techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL), yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.

76 citations

Journal ArticleDOI
TL;DR: In this article, a variable-mesh combination of the expanded-node transmission line matrix (TLM) and finite-difference-time-domain (FD-TD) methods for solving time-domain electromagnetic problems is described.
Abstract: A variable-mesh combination of the expanded-node transmission line matrix (TLM) and finite-difference-time-domain (FD-TD) methods for solving time-domain electromagnetic problems is described. It retains the physical process of wave propagation and the numerical stability of the former and it has the computational efficiency of the latter. This full-wave finite-difference transmission line matrix (FD-TLM) method utilizes transmission lines of differing impedances to implement a three-dimensional variable mesh, which makes practical the simulation of structures having fine details, such as digital integrated circuits (ICs). Circuit models for lumped resistors, capacitors, diodes, and MESFETs have been developed and included for use in simulating digital and microwave ICs. The validity of the variable mesh implementation is verified by comparing an FD-TLM simulation of a picosecond pulse generator structure with electrooptical measurements, and the validity of the device model implementation is verified by comparing an FD-TLM simulation of a MESFET logic inverter with a SPICE simulation. >

76 citations

Proceedings ArticleDOI
06 Apr 2009
TL;DR: Simulations demonstrate that the model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform and can be efficiently used to design hybrid MTJ/CMOS circuits.
Abstract: The integration of Magnetic Tunnel Junctions (MTJ) above CMOS circuits in embedded Magnetic RAM (MRAM) or Magnetic FPGA (MFPGA) could bring to digital circuits major advantages associated to non-volatile capability such as instant on/off, multi-context FPGA and zero standby power consumption. A complete simulation model for the hybrid MTJ/CMOS design is presented in this paper. Based on the recently demonstrated Spin-Transfer Torque (STT) writing approach which promises to lower the switching current down to ∼120uA, we have added to the previous static model the dynamic behaviors as well as the switching probability and the thermal effects. The model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform. Many experimental parameters are included in this model to improve the simulation accuracy. Simulations demonstrate that the model can be efficiently used to design hybrid MTJ/CMOS circuits.

76 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202369
2022156
2021171
2020255
2019255
2018250