Topic
Digital electronics
About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.
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TL;DR: The DELIGHT.SPICE tool, a union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program, is presented, yielding substantial improvement in circuit performance.
Abstract: DELIGHT.SPICE is the union of the DELIGHT interactive optimization-based computer-aided-design system and the SPICE circuit analysis program. With the DELIGHT.SPICE tool, circuit designers can take advantage of recent powerful optimization algorithms and a methodology that emphasizes designer intuition and man-machine interaction. Designer and computer are complementary in adjusting parameters of electronic circuits automatically to improve their performance criteria and to study complex tradeoffs between multiple competing objectives, while simultaneously satisfying multiple-constraint specifications. The optimization runs much more efficiently than previously because the SPICE program used has been enhanced to perform DC, AC, and transient sensitivity computation. Industrial analog and digital circuits have been redesigned using this tool, yielding substantial improvement in circuit performance. >
367 citations
TL;DR: In this article, the Coulomb blockade was used to block all tunnel events near zero bias voltage in series arrays of ultrasmall junctions, an effect that has come to be known as the ‘Coulomb blockade.
Abstract: A finite charging energy, e2/2C’, is required in order to place a single electron onto a small isolated electrode lying between two tunnel junctions and having a total capacitance C’ to its external environment. Under suitable conditions, this elemental charging energy can effectively block all tunnel events near zero bias voltage in series arrays of ultrasmall junctions, an effect that has come to be known as the ‘‘Coulomb blockade.’’ This article outlines a new approach to the design of digital logic circuits utilizing the Coulomb blockade in capacitively biased double‐junction series arrays. A simple ‘‘on’’/‘‘off ’’ switch is described and complementary versions of this switch are then employed to design individual logic gates in precise correspondence with standard complementary metal–oxide semiconductor architecture. A planar nanofabrication technique is also described that may eventually allow the integration of Coulomb blockade logic onto conventional semiconductor chips, thereby realizing hybrid i...
363 citations
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Abstract: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. This paper presents a method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability.
359 citations
01 Nov 1978
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as discussed by the authors, and the testability is also related to how well the internal nodes can be controlled and observed.
Abstract: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively. This paper presents a method for analyzing digital circuits in terms of six functions which characterize combinational and sequential controllability and observability.
349 citations
TL;DR: An extension of the effective capacitance equation is proposed that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation, for the "effective load capacitance" of a pc interconnect.
Abstract: With finer line widths and faster switching speeds, the resistance of on-chip metal interconnect is having a dominant impact on the timing behavior of logic gates. Specifically, the gates are switching faster and the interconnect delays are getting longer due to scaling. This results in a trend in which the RC interconnect delay is beginning to comprise a larger portion of the overall logic stage delay. This shift in relative delay dominance from the gate to the RC interconnect is increased by resistance shielding. That is, as the gate "resistance" gets smaller and the metal resistance gets larger, the gate no longer "sees" the total net capacitance and the gate delay may be significantly less than expected. This trend complicates the timing analysis of digital circuits, which relies upon simple, empirical gate delay equations for efficiency. In this paper, we develop an analytical expression for the "effective load capacitance" of a pc interconnect. In addition, when there is significant shielding, the response waveforms at the gate output may have a large exponential tail. We show that this waveform tail can strongly influence the delay of the RC interconnect. Therefore, we propose an extension of the effective capacitance equation that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation. >
347 citations