Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Automatic test pattern generation for crosstalk glitches in digital circuits

Abstract: As clock speeds of current deep submicron design technologies increase over 1 GHz and metal line spacings narrow, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designer to test the effects before taping out the designs. Unfortunately, conventional tests for stuck-at or delay faults are not guaranteed to expose potential crosstalk effects. This paper presents an efficient methodology for generating test vectors to detect crosstalk glitch effects in digital circuits. The ATEG (Automatic Test Extractor for Glitch) algorithm uses the multiple backrace technique, and uses a "forward-evaluation" technique in its backtacking phase which searches for the "right" entry to select by propagating "suggested values" to minimize the number of backtracks. In the glitch propagation phase, we employ a criterion function which gives a metric for determining the propagation of a transitional signal at a given gate. Our experiments show that ATEG efficiently generates test vectors to create glitches at candidate nodes.

CMOS Differential Ring Oscillators: Review of the Performance of CMOS ROs in Communication Systems

Abstract: The integrated differential ring oscillator (DRO) in complementary metal oxide semiconductor (CMOS) technology has been used in numerous products for a long time. Its presence has been extended to high-speed clock and data recovery (CDR) circuits for optical communication, analog and digitally controlled oscillators, frequency dividers of high-frequency synthesizers, clock generators of digital circuits, analog-to-digital converters (ADCs), and many more applications [1]-[5]. Implementations of these ring oscillators are seen in emerging technologies such as ultrawideband (UWB) and radio frequency identification (RFID) as well as wireless sensor networks (WSNs) and short-range communication devices [6], [7]. The DRO is a good design choice for integrated circuit (IC)designers because of its continued use in different bulk CMOS technologies. This article presents implementation techniques and performance comparisons of the DRO as a CMOS voltage-controlled oscillator (VCO) in low radio frequency (RF) bands, along with presentation and discussion of a number of circuit approaches.

A digital read/write channel with EEPR4 detection

Abstract: This device increases the inter-symbol interference (ISI) manageable in a magnetic-media read channel. It re-configures analog and digital circuits by registers to optimize read and write channels. The 51 mm/sup 2/ device is fabricated in a standard 0.8 /spl mu/m single-poly double-metal CMOS process, and contains 128 k transistors. No external components are required for operation other than standard decoupling capacitors. Most of the circuits are active while reading data from the media (data mode), and techniques such as the use of differential analog structures, dedicated supply routes and substrate connections, and shields are employed to control digital interference. >

Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits

Abstract: An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.