Digital electronics

About: Digital electronics is a research topic. Over the lifetime, 10354 publications have been published within this topic receiving 153532 citations.

Evolving digital circuits using hybrid particle swarm optimization and differential evolution.

Abstract: This paper presents the evolution of combinational logic circuits by a new hybrid algorithm known as the Differential Evolution Particle Swarm Optimization (DEPSO), formulated from the concepts of a modified particle swarm and differential evolution. The particle swarm in the hybrid algorithm is represented by a discrete 3-integer approach. A hybrid multi-objective fitness function is coined to achieve two goals for the evolution of circuits. The first goal is to evolve combinational logic circuits with 100% functionality, called the feasible circuits. The second goal is to minimize the number of logic gates needed to realize the feasible circuits. In addition, the paper presents modifications to enhance performance and robustness of particle swarm and evolutionary techniques for discrete optimization problems. Comparison of the performance of the hybrid algorithm to the conventional Karnaugh map and evolvable hardware techniques such as genetic algorithm, modified particle swarm, and differential evolution are presented on a number of case studies. Results show that feasible circuits are always achieved by the DEPSO algorithm unlike with other algorithms and the percentage of best solutions (minimal logic gates) is higher.

Routable technology mapping for LUT FPGAs

Abstract: A routing-driven technology mapper for lookup-table, (LUT)-based field-programmable gate arrays (FPGAs) is presented. The approach is based on performing mapping aimed at routing feasibility. For an FPGA of given size (number of LUTs), the logic being implemented is distributed in such a manner that the total wire length is minimized and the routing resources are not overutilized. Simulated annealing is used to perform mapping, placement, and global routing in tandem. The algorithm can handle both combinational and sequential logic circuits, and has been implemented for combinational circuits. Experiments on MCNC benchmark circuits show encouraging results. >

A "flying-adder" architecture of frequency and phase synthesis with scalability

Abstract: Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on "synchronous" design principle. Clock is the most important issue in these designs. Frequency and phase synthesis is closely related to the clock generation. A frequency and phase synthesis technique based on phase-locked loop is proposed in that delivers high performance, easy integration, and high stability. However, there are problems associated with this architecture, such as: 1) its highest deliverable frequency is limited by the speed of the accumulator and 2) the phase synthesis circuitry will not work well in certain ranges (dead zone) and in certain conditions (dual stability). This paper presents an improved architecture that addresses these problems. The new frequency synthesis circuitry has scalability for higher output frequency. It also has an internal node whose frequency is twice that of output signal. When duty cycle is not a concern, this signal can be used directly as clock source. The new phase synthesis circuitry is free of "dead zone" and "dual stability." The improved architecture has better performance, is simpler to implement, and is easier to understand.

Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

Abstract: The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.

A Programmable Logic Approach for VLSI

Abstract: This paper explores the use of a proposed programmable storage/logic array (SLA) chip as a general purpose universal logic element for digital computers. The SLA is compared to other programmable logic arrays in implementation and utilization, showing how it permits construction of complete digital subsystems on one chip without sacrifice in programmability. When compared with other contending very large-scale integrated technology (VLSI) approaches, such as microprogrammed processors and gate arrays, the SLA offers an attractive combination of cost, performance, and ease of implementation.