Showing papers on "Digital signal published in 1970"

On digital single-sideband modulators

Abstract: This paper concerns digital single-sideband modulators with analog inputs and outputs. A group of 12 modulators is treated as a single system, with analog-to-digital converters at 12 input ports and a digital-to-analog converter at a single output port. Tradeoffs are obtained between computational parameters. Substitution of digital counterparts for the phase shifters and product modulators in 12 analog Hartley modulators gives a simple program. However, operation in real time requires quite a large number of multiplications per second. A similar digitalization of 12 Weaver modulators requires even more multiplications. However, the 12 Weaver modulators can be transformed as a system, to reduce the multiplication rate for the Hartley system by a factor 4 . The cost is an increase in scratch pad storage and a more complex program.

Digital signal generator synthesizer

Abstract: Illustrative embodiments of the present invention shown and described include digital logic systems for generating signal waveforms of desired types. A relatively few digital logic modules are connected to generate a variety of desired waveshapes in a linear manner. Apparatus for generating rectangular waves, saw-tooth waves, sine waves, and sine waves having amplitude, pulse, frequency and phase modulation applied to them are disclosed.

Digital waveform generator

Abstract: A digital waveform generator for providing digital waveforms particularly of the sinusoidal type. The invention comprises means for providing a sequence of digital numbers whose values vary in accordance with the phase versus time function of the sinusoidal waveform to be generated. The function of time may be linear or nonlinear in accordance with the desired waveform. The sequence of numbers is utilized to address a digital memory wherein is stored the digital sinusoidal functional values corresponding to the digital phase values. As the sequence of phase numbers addresses the memory in accordance with the function of time, the corresponding sequence of sinusoidal numbers are provided by the memory, thus generating the desired digital waveform. Two embodiments are disclosed, one of which utilizes two registers for controlling the frequency and phase, respectively, of the output waveform. The other embodiment utilizes a difference equation computer to approximate the phase function by a recursively generated polynomial function of time.

System for frequency modification of speech and other audio signals

Abstract: A system for multiplying the frequencies of a speech signal, or other audio signal, by a given multiplication factor, comprising an analog-digital converter for converting an audio signal to a digital signal having a bit rate f1 and means for temporarily storing that digital signal. The system further comprises apparatus for reading out the stored digital signal, in groups of n digits, at a bit rate f2, with means for synchronizing the readout apparatus to connect the groups of n digits in sequence. A digital-analog converter uses the digital readout to develop a speech signal modified in frequency in accordance with the rate f1/f2 but having the same time span as the original speech signal.

Digital data scrambler-descrambler apparatus for improved error performance

Abstract: The output of a digital encoder is delivered to a digital data scrambler prior to being encoded as a multilevel (e.g., quaternary) signal for transmission. The digital input to the scrambler is operated on in a deterministically randomized manner which results in a digital output that is modified so as to insure the virtual elimination of unwanted DC shift in the multilevel signal. At the receiving end of the transmission facility, the inverse operation, again deterministic, returns the received digital signal to its original form prior to the decoding operation. In the preferred embodiment, the scrambler (and descrambler) comprises a one-cell feedback shift register with a modulo-2 adder in the feedback coupling.

Apparatus for deriving synchronizing pulses from pulses in a single channel pcm communications system

Abstract: A method and apparatus is disclosed for bit synchronization of a received PCM communications signal, without requiring a separate synchronization channel in the communications signal by digital correlation of the received square-wave signal with a predetermined number of phase displaced replicas of its expected form. Each phase displaced replica is correlated with the input signal to determine which phase displaced replica produces the largest correlation signal. In carrying out the correlation of the square-wave signal with a given phased displaced replica, the two levels of the replica corresponding to the +1 and -1 binary values of the input signal are employed as sign signals to control the arithmetic addition or subtraction of the input signal binary values to the contents of an accumulator. The binary values of the input signal are produced by means for sampling and converting the input signal into +1 and -1 values. A plurality of samples of the input signal are thus accumulated during each cycle of a number of input signal cycles to develop a correlation value.

Signal conditioner and bit synchronizer

Abstract: A signal conditioning circuit for use in a digital communication system for restoring the waveform of a received signal which may have been degraded during transmission. The incoming signal is applied to a variable gain amplifier, filter and direct current amplifier and the resulting output signal is compared both positively and negatively to predetermined reference values. Where the output signal deviates from these two references, a digital control signal is developed for adjusting the gain of the variable gain amplifier and the baseline of the direct current amplifier such that the output pulse conforms to a predetermined value.

Color television system including additional information signals in pulse code on a special color burst

Abstract: A multiple transmission system of one or more information signals on a color television signal, wherein at least one information signal, such as a voice signal, is sampled and coded to form a coded digital signal representing the information signal. The coded digital signal consists of pulses having a bit frequency and a phase identical with the frequency and the phase of the color burst signal of the color television signal. Successive sample values of said coded digital signal are transmitted during the period of the horizontal blanking signal of the color television signal with the phase of the color burst signal so that the superposed coded digital signal represents also the information of the color burst signal.

Electrical digital display tonometer

Abstract: Apparatus for measuring displacement is disclosed which includes a prehensible member including a transducer for developing an analog electrical signal whose value is a function of the displacement to be measured and digital display means for visually displaying a digital reading of such value. A stationary unit remote from the prehensible member is also provided which includes conversion means for converting the analog signal into a suitable digital signal for display in the digital display means. A flexible cord is provided interconnecting the prehensible member and the stationary unit for conducting the analog signals from the transducer to the conversion means and the digital signal from the conversion means to the digital display means.

Digital signal linearizer

Abstract: A digital signal linearizer for obtaining a linear digital output from a non-linear input. The input voltage is a non-linear representation of a quantity, such as temperature as measured by a thermocouple sensor. A voltage controlled oscillator converts the input voltage to a pulse train having a pulse rate which is a linear representation of the input voltage, but like the input voltage, is a non-linear representation of the measured quantity. The pulses are connected through a NAND gate to programmable DIVIDED N frequency divider for fixed repeated intervals. Hence, the number of pulses passed depends directly on the repetition rate of the oscillator output pulses. Since the voltage, and hence pulse rate v. Quantity measured characteristics of the sensor are known, the divider is programmed to provide a division factor n which varies over different segment of the range of interest so that the output pulse count from the divider is linearly related to the quantity being measured.

Apparatus for recognizing graphic symbols

Abstract: An optical character recognition device is disclosed wherein a character is scanned by a cathode ray tube along a plurality of parallel scan lines and a photo-detector derives an analogue electrical signal proportional to the intensity of the light signal output from each scanned point. The derived analogue signals are compared with a plurality of threshold values, and an optimum threshold is selected. The resulting digital signal is then compared with pre-established graphic signals to provide a recognition symbol identifying the character. Means are also provided to command a re-examination of an unrecognized signal by selecting a different threshold value. A logical filter apparatus is also provided to operate on the binary value assigned to the point under examination and the surrounding points and to assign to the examined point a binary signal level depending at least in part on the signal levels of the surrounding points. This logic filter circuit also includes means for detecting end points in lines and for detecting and eliminating break points in lines by comparing signal bits corresponding to the points surrounding the point examined to a pre-established set of conditions.

System for phase locking on a virtual carrier

Abstract: The present invention is directed to a phase lock system which can derive a demodulating carrier reference signal for use in a suppressed carrier quadrature, amplitude modulating digital data transmission system which does not require the transmission of a low level carrier or pilot tones. The system operates by multiplying the equalized received signal in each channel by the decoded n-level data signal of the other received channel, subtracting the products and dividing the result by the sum of the squares of the data signal levels to arrive at an error signal which is proportional to the phase error between the demodulating carrier reference signal and the suppressed transmitting carrier. The derived error signal can be made independent of data signal level values and the received signal levels even in the presence of severe intersymbol interference. The derived phase error signal is fed back to a variable oscillator providing the demodulating carrier reference signal to change the phase of the reference signal so as to reduce the error signal towards zero.

Mass flow monitoring system and method

Abstract: A densitometer has an acoustically shielded, temperature insensitive, tuning fork-type density sensing element which incorporates certain design factors and is driven at its natural frequency by a regenerative drive circuit employing piezoelectric drive and pickup crystals. A mass flow rate computing method is embodied in a computing system having electronic multiplication means which operates in dependency upon volume flow rate information in a digital signal and which is controlled by the output from a signal sampling and density computing circuit that operates in dependency upon a digital signal having a frequency that varies as an inverse linear function of the sensed density condition. During a sampling period, the latter circuit gates a clock signal to a counter preset to provide a registered count proportional to the density condition during the sampling period and the registered count is transferred to a memory having an output that controls the output of the electronic multiplication means between successive count transfers.

Ladderless digital-to-analog converter

Abstract: A charge-gated, ladderless, digital to analog (D to A) converter for converting a digital input signal into an analog output signal. The digital input signal is provided to an analog signal generating circuit, including a counter, which, upon command, generates an analog signal in the form of a pulse width which is a representation of the magnitude of the digital input signal and is a proportion of a predetermined maximum pulse width. The analog signal generating circuit includes means for applying a predetermined reference signal to the input of an integrating circuit for a period of time equal in duration to the pulse width representation of the digital input signal. The output from the integrator is received and stored upon command by storage means including a storage capacitor, to provide the analog output signal. The analog output signal is then connected to the input of the integrator for a period of time equal to the full scale integration time. In effect, when applied to the integrator, the output signal is integrated while the signal from the previous conversion remains stored on the integrator capacitor so that at the end of the integration, the signal at the integrator output is nominally equal to zero. The amount that the output signal from the integrator differs from zero at this time represents the error in the output signal of the converter and, in the subsequent conversion cycles, this error signal acts to correct the error.

Digital control system for ac to dc power conversion apparatus

Abstract: A digital control system for controlling the conversion of electric power from AC power to DC power for delivery to a load. A digital command signal is compared with a digital feedback signal indicative of motor speed so as to generate a digital error signal. A phase detection circuit examines the three phases of the AC source so as to synchronously load the digital error signal into the digital firing circuit associated with each phase at the appropriate time. The digital firing circuits include a plurality of reversible counters which count up during one portion of an excitation cycle and count down for another portion of an excitation cycle. When counting up, if a reversible counter reaches a preset number, a firing pulse is generated for a positively poled SCR. On the other hand, if the reversible counter is counting down, when the counter reaches a preset number, a firing pulse is generated for a negatively poled SCR.

Fluid operated stepping motor

Abstract: A fluid operated stepping motor has a rotor with a plurality of ramps. A plurality of pistons are positioned in the stator of the motor on opposite sides of the rotor in alignment with the rotor axis to rotate the rotor. A logic circuit is adapted to accept a digital signal to rotate the rotor a discrete amount in either a clockwise or counterclockwise direction. The logic circuit actuates only certain pistons which stroke to rotate the rotor. The position of the rotor determines which of the pistons will be stroked upon receipt of the next signal by the logic circuit.

Phase detection system for at least one digital phase-modulated wave

Abstract: A phase detection system for at least one digital phase-modulated wave, in which two products of a phase-modulated digital signal and two reference carrier waves each having the same frequency as the phase-modulated digital signal and a phase difference 90 DEG therebetween are at first produced, so that a converted value which is a function of a phase difference between the phase-modulated digital signal and one of the reference carrier waves is found by integrating respectively the two products or by passing the two products in respective low-pass filters. The phase detection of the phase-modulated wave is performed by comparing the converted value with a reference phase. Compensation means may be further provided to compensate phase error in the converted value.

Offset size adjustment circuit for grinding machines

Abstract: An automatic machine, which includes a gage mechanism, for grinding workpieces having axially spaced portions of different diameters is disclosed. The gage mechanism, which is used to determine the diameter of each workpiece portion to assure that the workpiece is within certain tolerances, includes a workpiece engaging element or caliper of the chordal type which supplies a signal, indicative of the sensed diameter of a workpiece portion, to a summing network. The summing network also receives a signal from a digital to analog converter arranged to convert a digital signal from a card reader into an analog signal indicative of a desired diameter of a workpiece portion. An analog size offset circuit is arranged to supply an offset signal to the digital to analog converter. The offset circuit provides, in addition to a settable common offset signal, an additional programmed offset signal which is derived from a second analog to digital converter supplied with digital signals from thumbwheel switches which receive enabling signals from a program sequence controller. The controller also supplies enabling signals to the card reader associated with the first-mentioned digital to analog converter.

Quadrature injection control circuit

Abstract: A data signal communication system including an analog signal transmitter and a receiver for converting the analog signal levels to digital form. The receiver employs an automatic gain control loop including means for generating an error signal related to the difference between the analog input and the analog equivalent of a digital output. The error signal is used to control both loop gain and the quantity of a quadrature component which is combined with the data signal within the automatic gain control loop.

Digital signal reception system

Abstract: A digital system reception signal comprises an error detection circuit for detecting an error code contained in the transmitted coded signal. Upon the detection of the error code, the received composite digital signal of the repetition period or scanning line replaces the stored coded signal of the previous repetition period.

Test apparatus for digital repeaters

Abstract: Apparatus is disclosed that determines whether a digital repeater circuit correctly reproduces an input signal comprised of sequential groups of digital signals wherein each group includes a preset number of digital signals. A counter circuit receives a count corresponding to the number of digital signals in a group, and an error signal is produced in the event that the count at the end of a group of signals does not correspond to the preset number.

Digital privacy system

Abstract: A digital voice-privacy system uses a delta modulator to convert voice information to digital data which then is encoded by combining the output of the delta modulator with a digital signal derived from selected stages or a shift register and a programmable code memory with the resultant data train being fed back as the input signal train for the shift register. The output of the last stage of the shift register is the encoded data. The data is decoded by a similar system, with the received signals being supplied to the input of a shift register and programmable code memory circuit comparable to the one used in the encoder to form a decoding signal which is combined with the encoded digital data to provide an output to a delta demodulator, the output of which then is the desired decoded voice information.

Data transferring system utilizing frame and bit timing recovery technique

Abstract: The transmitter-encoder of the data transferring system includes a combiner which develops an information signal by sequentially sampling the output states of a plurality of data sources. A timing signal generator develops bit and frame timing control signals for the combiner and a carrier and two pilot signals which are synchronized with the control signals to facilitate timing recovery at a receiver-decoder of the data transferring system. A composite signal comprised of an encoded information signal, carrier and pilots is transferred to the receiver through a medium which might produce abnormal information, such as an undesired frequency shift or phase perturbations, in the signal at the receiver-decoder input. The receiver includes circuitry which derives the carrier signal to facilitate demodulation. A demodulation circuit establishes the difference of each of the pilot signals and the encoded information signal from the carrier to produce two difference mixing signals and a difference information signal which have any frequency shift caused by the medium eliminated therefrom. One of the two difference mixing signals is utilized to reconstruct the bit timing signal and the other mixing signal along with a control signal derived from the bit timing signal is utilized to provide a frame timing signal which does not have any frequency or phase ambiguity. The bit and frame timing signals operate a bit separator included in the receiver which selectively channels the decoded data from the information signal to each of a plurality of data utilization devices corresponding to each of the data sources. A monitor signal which is synchronized with the data signal and which has a known pulse code may form part of the information signal to facilitate secure data transmission.

Active submarine target echo synthesizer

Abstract: Apparatus wherein an active incoming sonar signal is synthesized by means including a spaced array of receiver transducers to provide a carrier frequency and a digital signal, said digital signal being applied to address a memory means including a core memory in which submarine signatures are stored for retrieval in relation to the type of submarine and aspect angle thereof and which also includes a digital to analog converter means. The outputs of said analog converter means being applied to modulate a carrier wave signal derived from a tone burst to carrier wave converter and further modulated by range data from a range translator to activate transducer means to provide a reflected submarine target sonar signal representative of a selected type submarine at an aspect angle and range corresponding to said incoming active sonar signal.

Method and apparatus for detecting errors read from moving-magnetic-storage device with digital interface

Abstract: A data signal read from magnetic tape is converted from an analog signal into a digital signal by hard limiting. This hardlimited data signal is combined with an indication as to whether the amplitude of the digital signal is above a predetermined threshold and then passed to the control unit operating with the tape drive. The control unit, in turn, detects the data, checks for parity error, phase error, and amplitude error and provides control signals back to the tape drive. These control signals are used to change the predetermined threshold used by the tape drive. The predetermined threshold is changed by these control signals in accordance with detection of a history of good data and in accordance with errors in the record block.

Digital circuit discriminator for frequency-shift data signals

Abstract: FSK data signals are applied to a phase-locked loop whose binary signal output has an average amplitude which varies with the frequency of the incoming data signal. A zero-crossing detector produces a pulse for each zero crossing of the binary signal and the pulses are processed by a transversal digital filter having finite memory and arranged to provide triangular weighting to each input pulse. The baseband signal is then recovered from the filter output. In one embodiment, the zero-crossing detector and the transversal filter are advantageously arranged to be time shared by a plurality of FSK signal channels.

Two phase encoder system for three frequency modulation

Abstract: A multiphase encoder translates the bits of a Non-Return-to-Zero digital signal into a three frequency self-clocking having a data transition at the center of a binary ONE bit and a data transition between successive binary ZERO bits.

Adaptive digital automatic gain control for mti radar systems

Abstract: An adaptive digital automatic gain control (DAGC) system is disclosed for pulsed radar moving target indicator (MTI) systems to reduce the input dynamic range requirements of a data processing and display system by dividing each range sweep into a number of range elements of one or more range bins, comparing the signal level in each range element to a selected reference level, and providing a digital error signal indicating whether or not the video signal is greater than the reference signal. The radar video signal is processed by an MTI filter, the output of which is compared with a selected reference level to similarly provide digital error signals for AGC control based on not only the raw radar video signal, but also the MTI video signal. These digital error signals are integrated separately for each range element, thereby developing for each range element an AGC signal in digital form based on the past history in the raw radar video signal and the MTI video signal over a continuous succession of range sweeps. After conversion into analog form, these digital AGC signals developed for all range bins of a given sweep are filtered by a low pass filter to provide an analog AGC signal which is smooth over approximately 16 range bins. A noise AGC signal is similarly developed and combined with the radar video and MTI video AGC, but at a much slower rate of one sample per azimuth scan.

Method for synchronizing digital signals and an arrangement for carrying out the method

Abstract: The invention relates to a method and an arrangement for synchronizing blocks of digital signals transferring information from a transmitter to a receiver. A cyclically repeated counting process the greatest value of which corresponds to the number of bits in the block controls a parallel-series conversion on the transmitter side and a series-parallel conversion on the receiver side. A cyclically generated synchronizing word formed of ones and zeros is logically superposed on the digital signal on the transmitter side and on the receiver side the same synchronizing word is again logically superposed on the combined signals in order to restore the original digital signal. During intervals occurring necessarily in continuous speech the synchronizing word appears alone and is identified and the number of its occurrence is counted. After a definite number occurrences of the synchronizing word a control pulse is generated which starts the cyclically repeated counting process on the receiver side.

Digital equalizer in which tap adjusting signals are derived by modifying the signal code format

Abstract: An all digital multitap transversal filter equalizer system is disclosed in which a received data signal is sampled at a predetermined rate. Each sample of the data signal is converted into a 10-bit serial digital word. The 10-bit word is multiplied by a second digital word successively at each tap to provide data for composite output data words. It has been found that by converting the composite output data word into one''s complement format, error magnitude and error polarity signals can be derived for adaptive adjustment without additional equipment.