Showing papers on "Digital signal published in 1978"

Broadcast acknowledgement method and system

Abstract: A broadcast acknowledgement method and system wherein a digital information signal, generated in order to indicate the content with regard to a present broadcast program (for example, a commercial broadcast program on television, radio or CATV), is superimposed on the voice signal of said program for broadcast and the composite signal transmitted to the receiving station, where it is processed to retrieve the digital information signal. Thereby, it can be confirmed whether or not the particular program has been broadcast or not. The method generally comprises the steps of removing the particular frequency band of the voice signal, generating the digital information signal by using some of the desired frequency signals within the particular frequency band of the voice signal, superimposing the digital information signal on the voice signal, transmitting the composite signal, extracting the digital information signal from the received signal at the receiving side, and processing the digital information signal so extracted to identify the particular program broadcast, and thus to obtain broadcast acknowledgement information such as sponsor's name, performers' name, time of broadcasting, etc. The broadcast acknowledgement system comprises, in several embodiments, a voice amplifier, band elimination filters, digital information generation circuit, various signal generators, and a mixing circuit; and, in another embodiment, a voice amplifier, band elimination filters, a digital information generation circuit, and a selector circuit.

Applications of digital signal processing

Abstract: Applications of digital signal processing , Applications of digital signal processing , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Quadrantal symmetry associated with two-dimensional digital transfer functions

Abstract: The class of two-dimensional (2-D) digital transfer functions which possess quadrantal symmetry in their frequency responses is derived. Application of this class in the design of 2-D recursive digital filters is indicated.

Digital radio paging communication system

Abstract: A digital paging communication system including a transmitter and a plurality of receivers is disclosed. The transmitter generates a preamble digital signal, a calling digital signal and an end mark digital signal in a predetermined sequence. Each receiver demodulates a received signal into the preamble digital signal, calling digital signal and end mark digital signal. These signals are separately detected in synchronism with a recovered clock signal. Power is supplied to the radio frequency, intermediate frequency and demodulator sections of the receiver intermittently until such time as the calling signal of the receiver is detected, after which power is supplied continuously until an end mark signal is detected. The intermittent operation is a battery saving feature.

Operations on delta-modulated signals and their application in the realization of digital filters

Abstract: A new method is proposed with which it is possible to find a delta-modulated signal of the half sum of two analogue signals through a direct operation on their delta-modulated form. With a direct operation it is also possible to form a delta-modulated signal of the product of an analogue signal by a constant. The resulting modulated signal includes an error which is generally considered negligible. The hardware implementation of the method is both, simple and modular employing only conventional full adders and D-flip-flops. This leads to the possibility of realization of digital filters with straight delta-modulated input and output signals which are not intermediately transformed. Multiplexing for changing coefficients is also possible.

Recognition of a received signal as being from a particular transmitter

Abstract: A system for recognizing a received encoded signal as being from a particular transmitter is disclosed. An encoder encodes a signal to have a predetermined sequence of pulses of three different predetermined sequence of pulses of three different predetermined durations within a constant bit interval in accordance with a trinary code; wherein each of the different predetermined durations corresponds to a different bit. A decoder is coupled to the receiver for recognizing the received encoded signal as being from the particular transmitter includes a programmable digital logic signal generator that is programmed in accordance with the trinary code for generating a programmed digital logic signal having a predetermined sequence of different digital words corresponding to the predetermined sequence of pulses of different predetermined durations in the transmitted encoded signal; a code converter for converting the received encoded signal to a decoded digital logic signal having digital words in accordance with the selected code by measuring and comparing the relative durations of the pulse and the non-pulse time during each bit interval; a comparator for comparing the decoded digital logic signal with the programmed digital logic signal; and a control logic circuit coupled to the programmable signal generator, the code converter and the comparator for synchronizing the programmed digital logic signal with the decoded digital logic signal and for recognizing the received encoded signal as being from the transmitter when said comparison indicates a predetermined number and sequence of valid comparisons between the decoded digital logic signal and the programmed digital logic signal.

High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing

Abstract: Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.

Linearized digital thermometer

Abstract: A digital thermometer uses a microprocessor computer containing stored information relating to the response characteristics of a transducer to supply a measurement of temperature. The transducer is preferably a thermistor whose resistance varies in a predetermined and nonlinear relation to its temperature. The microprocessor computer includes a read-only memory which has been preprogrammed with piece-wise linearized information approximating the nonlinear relation of resistance and temperature of the thermistor. A current source develops a voltage across the thermistor which is related to the temperature of the thermistor. The voltage across the thermistor is converted into a digital signal, and the digital signal is related to the piece-wise linearized information stored. The temperature equivalent is calculated from a first order algebraic equation determined by the relationship of the digital signal to the stored information.

System and method for regulating power output in a microwave oven

Abstract: A method and control system for regulating the output power of a magnetron in a microwave oven having a food heating cavity, a magnetron, and a waveguide coupling the magnetron to the heating cavity. The reflection coefficient within the waveguide is measured and a control signal is generated to switch the magnetron between first and second levels of power output when the reflection coefficient reaches a pre-determined value indicating that the food item within the oven has begun to defrost. In the preferred embodiment, the present invention incorporates digital signal processing utilizing a microprocessor to calculate the reflection coefficient and generate the control signal based upon digital signal inputs that are a function of the detected microwave energy within the waveguide.

System and method for speech recognition

Abstract: A system and method for speech recognition provides a means of printing phonemes in response to received speech signals utilizing inexpensive components. The speech signals are inputted into an amplifier which provides negative feedback to normalize the amplitude of the speech signals. The normalized speech signals are delta modulated at a first sampling rate to produce a corresponding first sequence of digital pulses. The negative feedback signal of the amplifier is delta modulated at a second sampling rate to produce a second sequence of digital pulses corresponding to amplitude information of the speech signals. The speech signals are filtered and utilized to produce a digital pulse corresponding to high frequency components of the speech signals having magnitudes in excess of a threshold voltage. A microprocessor contains an algorithm for detecting major slope transitions of the analog speech signals in response to the first sequence of digital signals by detecting information corresponding to presence and absence of predetermined numbers of successive slope reversals in the delta modulator producing the first sequence of digital pulses. The algorithm computes cues from the high frequency digital pulse and the second sequence of pulses. The algorithm computes a plurality of speech waveform characteristic ratios of time intervals between various slope transitions and compares the speech waveform characteristic ratios with a plurality of stored phoneme ratios representing a set of phonemes to detect matching therebetween. The order of comparing is determined on the basis of the cues and a configuration of a phoneme decision tree contained in the algorithm. When a matching occurs, a signal corresponding to the matched phoneme is produced and utilized to cause the phoneme to be printed. In one embodiment of the invention, the speech signals are produced by the earphone of a standard telephone headset.

Digital apparatus approximating multiplication of analog signal by sine wave signal and method

Abstract: A method and an apparatus are disclosed which employ digital techniques to approximate a multiplication of an analog signal by a sine wave of an appropriate frequency for detecting the analog signal The analog signal is converted to a digital representation which includes a binary sign bit and a plurality of binary magnitude bits The sign bit of the digital representation is selectively complemented by an inverting logic gate which operates under the control of a square wave having the appropriate frequency of the sine wave which is being approximated The selective complementation of the sign bit of the digital representation functions to multiply the digital representation by +1 or -1 as determined by the status of the square wave signal The resulting digital representation is latched at periodic intervals for further processing of the detected signal which results from the quasi digital multiplication

Equivalent standard volume correction systems for gas meters

Abstract: A self-contained correction unit operable in conjunction with a gas meter measuring an actual gas volume emits a digital output signal correlated to an equivalent standard gas volume therefor by correcting the actual gas volume for prevailing conditions of temperature and/or pressure. A temperature and/or pressure transducer is utilized which when exposed to the gas flow emits an analog voltage signal proportional to absolute values of the sensed parameter. By scaling the transducer output signal to a base condition voltage representing unity, a signal proportional to the desired correction is derived which is converted to a digital signal for supplying to a divider-counter. Within the divider-counter, a series of repetitive pulses corresponding to the actual volume measured by the meter is divided by the digital correction signal to yield a digital output signal of the corrected volume at the base condition for which correction was being sought.

Computer network, line protocol system

Abstract: A line protocol format with a low bit overhead provides for the high accuracy, asynchronous exchange of digital signal information between processing units in a supervisory control system having a central processing unit (CPU) and at least one remote processing unit (RPU).

Weight measuring method and apparatus thereof

Abstract: A weight measuring apparatus comprises a load cell for generating an analog signal corresponding to load applied, and A/D converter for converting an output signal from the load cell into a digital signal, a data processing unit which periodically reads a digital output signal out from the A/D converter to successively write the digital output signal into a first memory area of the memory and produces data corresponding to the weight of load applied to the load cell on the basis of plurality of digital data stored in the first memory area of the memory to write the data into a second memory area of the memory, and a display unit for displaying the data from the data processing unit The data processing unit compares a plurality of digital data stored in the first memory area As a result of the comparison, when a given number of or more digital data having the same values are included in the digital data stored in the first memory area, the digital data is produced as output data On the other hand, when the digital data having the same values fail to reach the given number, the digital data stored in the second memory area and the latest or newest one of the digital data read out from the A/D converter are compared When the difference between the two compared digital data exceeds a given value, the latest digital data is produced as output data When, on the other hand, the difference is less than the given value, the data stored in the second memory area is read out and outputted

D/a conversion system with compensation circuit

Abstract: A D/A conversion system with a compensation circuit comprises a D/A converter for converting a digital input signal into an analog signal and a memory for storing a compensation data used for the compensation of the output of the D/A converter at an address corresponding to the digital input signal The digital input signal is applied to the D/A converter and a signal corresponding to the digital input signal is applied to the memory The output of the D/A converter is adjusted on the basis of the compensation data read out from the memory

Digital single signal line full duplex method and apparatus

Abstract: A driver circuit that permits full duplex transmission of digital data on a single signal line includes means for enabling a receiver of a station having a transmitter and a receiver to ignore outgoing digital signals from the transmitter of the same station and receive incoming signals. The circuit includes means that combine the incoming and outgoing digital signals in the signal line to form a composite multi-level signal which shifts between predetermined amplitude levels and means that recover the incoming digital signals from the composite signal. An offset bias level is added within the receiver signal processing to the transmitter pulse level to reduce noise susceptibility. Using such a circuit a full duplex transmission system of a plurality of stations connected to a common single signal line is provided. Such a system can be operated in a broadcast mode wherein one station can transmit signals to the remainder of stations.

Multiple probe gage system

Abstract: A multiple probe gage system wherein the analog output signal of a plurality of probes is successively sampled, digitized and stored. The stored information is then digitally processed by a microprocessor to produce a digital signal which is a function of the analog output signals of selected probes.

Capacitive measuring system with automatic calibration

Abstract: In a device for continuously monitoring the characteristics of a moving filament, such as the denier of an extended synthetic yarn, by passing the filament through a capacitive sensor to develop an electrical signal representing an absolute measurement of the filament with reference to a prescribed datum, the problem of measurement signal drift arising from contamination of the capacitive sensor is obviated by developing compensating signals to be combined with the filament measurement signal. The compensating signals are digitally formed and stored, thereby eliminating drift in the compensating signals themselves. The compensating signals are developed in an auto-calibration circuit, including an auto-zero circuit and an auto-gain circuit, which receives the measurement signal from the capacitive sensor. While the sensor is vacant, the auto-zero circuit digitally counts clock pulses to generate a digital output, converts the digital output into an analog signal varying with the digital count, detects a prescribed comparison between the analog signal and the input measurement signal, and stops the clock pulse count at a zero compensating value when the comparison is detected. Then, the auto-gain circuit applies an unbalanced drive to the sensor, digitally counts clock pulses to generate a digital output, and varies the measurement signal gain with the digital output. The circuit detects a prescribed comparison between the gain-adjusted measurement signal and a standardized output signal, and stops the clock pulse count at a gain compensating value when the prescribed comparison is detected.

Lottery number generating method and apparatus

Abstract: A bank of counters is clocked at a relatively high repetition frequency by a clock oscillator. Each counter separately produces a sequence of digital signals which are transmitted at the clock oscillator frequency by a latch and a decoder/driver associated with the counter to a numeric display also associated with the counter. Consequently, the digital signals produced by each counter are separately displayed at the clock oscillator frequency. This frequency is sufficiently high to prevent recognition of a number on the display. A bank of manually operable momentary switches is associated with each latch. A brief audible tone is produced whenever a switch is operated. When operated, the switch temporarily disables the associated latch for a preselected interval of time. When disabled, the latch transmits only the digital signal currently stored in the latch to the display for the preselected interval of time. The preselected interval of time is sufficiently long to allow operator recognition of the number displayed. During the preselected interval of time, each counter continues to produce its sequence of digital signals. At the end of the preselected interval of time, the latch automatically resumes transmission of the digital signals produced by the associated counter to the display at the clock oscillator frequency.

Digital electric energy measuring circuit

Abstract: A digital electric energy measuring circuit for totalizing electrical power and energy usage from an alternating current supply by converting a voltage signal representing the current component into a pulse train signal whose frequency is proportional to the magnitude of the voltage, sampling that frequency to provide a digital value representing the current component, and then converting a voltage signal representing the voltage component into a second pulse train signal whose frequency is proportional to the magnitude of the voltage which is used to control the rate that the digitized value of the current component is successively added which provides an indication of electrical energy that is totalized and displayed

Wheel speed sensing system

Abstract: A wheel speed sensing system for a brake control system is characterized in that the periodic signal generated by a wheel speed transducer is used to trigger a series of digital signals having a frequency proportional to that of the periodic transducer signal. Clock signals are counted between a selected pair of digital signals to provide a digital measure of the time interval separating the digital signals and hence the period of the periodic signal. In a preferred embodiment the number of intervening digital signals separating the selected pair of digital signals is automatically chosen to maintain the time resolution of the measurement above a preselected value.

Low pass digital averaging filter

Abstract: A circuit for extracting a low frequency signal component from a composite signal is disclosed which uses a digital averaging technique for filtering out higher frequency components. An analog to digital converter receives a composite analog signal and provides a digital output signal. The composite analog signal is sampled during periodic intervals or sample periods. The digital output signal of the analog to digital converter is coupled to one input port of an adder/subtractor circuit and to the input of a sample register. The sample register stores the digital output signal and outputs the stored signal, delayed by a predetermined number of sample periods, to a second input port of the adder/subtractor. A storage register is used to store a running average which is equal to the sum of the digital signals received during the most recent predetermined number of sample periods. The average signal stored by the storage register is fed back to a third input port of the adder/subtractor. During each sample period, the adder/subtractor causes the current output of the analog to digital converter to be added to the previous average signal and causes the output of the sample register to be subtracted from the average signal. The result generated by the adder/subtractor is then stored in the storage register until the next sample period, during which the procedure is repeated.

Digital TDM-FDM Translator with Multistage Structure

Abstract: In this paper, a new digital signal processing algorithm for the digital TDM-FDM translator is proposed. The digital TDM-FDM translator, which performs a direct translation between two multiplex formats in the telephone network (time-division-multiplexing (TDM) and frequency-division-multiplexing (FDM)) by using digital techniques, has advantages in accuracy and stability of characteristics over equivalent analog equipments. However from the economical point of view, it largely depends on the cost reduction of semiconductor devices and LSI technologies. The proposed algorthm can be realized using only two digital filters and does not require product modulators or Fast Fourier Transform (FFT) processors. The required number of multiplications, which is closely related to the quantity of hardware, is considerably reduced by the multistage structure of this algorithm. The reduction in the kind of required digital hardware and the required number of multiplications makes it possible to efficiently utilize the new hardware realization techniques of digital filters or multipliers using read-only memories and simple logic devices. Since it is foreseen that cost reduction of memory devices will be more rapid than that of logic devices, the proposed algorithm is expected to be advantageous with regard to cost over existing algorithms where complex multiplier logic is required. The estimation of the computation rate is carried out with reference to a practical case. The computer simulation results are also shown.

Vehicular spreader with digital electronic ground speed link

Abstract: In a system for spreading material from a vehicle, the ground speed of the vehicle is sensed by a low torque transducer which generates a train of electrical pulses or digital signal having a repetition rate representative of the vehicle's ground speed. The digital signal energizes a stepper motor. The shaft of the stepper motor is coupled to a mechanical comparator which is also responsive to the speed of a conveyor, which delivers the material to be spread, for controlling the conveyor drive motor so that the speed of the conveyor tracks the ground speed of the vehicle even at very low speeds. Proportioning of the ground speed signals is accomplished electronically by a digital counter circuit. Override of the ground speed control signal is actuated by the operator. The override may require continued operator actuation; or the override, once actuated may last for a predetermined time or a predetermined distance travelled by the vehicle. In the latter two cases, the time and distance may be adjusted.

Color television receiver for simultaneous display of plural programs

Abstract: A color television receiver receiving two television signals of different channels, compressing the time axis of one of the television signals, and inserting this compressed television signal in a portion of the other television signal for displaying the pictures of the two channels on the same screen. In the receiver, the luminance signal, chrominance signal and synchronizing signal are derived from each of the received two television signals. A writing clock pulse signal is produced on the basis of one of the synchronizing signals for writing the luminance signal and chrominance signal in the corresponding television signal in a memory circuit, while a reading clock pulse signal is produced on the basis of the other synchronizing signal to read out the luminance signal and chrominance signal from the memory circuit in a relation in which these signals are compressed in the time axis. After the luminance signal and chrominance signal read out from the memory circuit are adjusted in their signal levels relative to the luminance signal and chrominance signal in the other television signal, a portion of the luminance signal and chrominance signal in the other television signal is replaced by the luminance signal and chrominance signal read out from the memory circuit so that the pictures of the two channels can be displayed on the same screen.

Digital apparatus for correcting a time-base error in a television video signal

Abstract: A digital time base corrector for correcting a time-base error in a television video signal, the video signal including a horizontal synchronizing signal and a color burst signal. The start of a write-in clock pulse oscillator is determined by a one-cycle portion of the color burst signal which has been extracted from the video signal in a prefixed phase relationship with the horizontal synchronizing signal. Oscillation frequency control at the write-in clock pulse oscillator is performed in response to the phase deviation of the write-in clock pulse from the extracted one-cycle burst signal portion. Phase-locking of the write-in clock pulse oscillator is performed in response to the phase difference, from the extracted one-cycle burst portion, of a selected one of first and second pulses, the first pulse occurring at the rate of the subcarrier signal and the second pulse occurring at the rate of the horizontal synchronizing pulse. Both pulses are obtained from the write-in clock pulse. The present invention adapts the time-base corrector to allow broader phase fluctuations of the write-in clock pulse with respect to the color burst and the horizontal synchronizing signal of the incoming video signal.

Vehicle fuel tank level indicator - uses low-pass filter to eliminate interference caused by vehicle movement mounted between tank transducer and indicators

Abstract: The indicating system has a transducer producing electrical signals and a means of suppressing the effects of vehicle movement on these electrical signals. This latter is a low pass filter located between the transducer in the tank and the fuel-level indicator. The transducer can be digital or analog; but if analog, the analog signal is converted into a digital signal by an A/D converter. In this case the low pass filter is also digital and is located between the A/D converter's output a and the fuel-level indicator. The LP filter provides a simple and cheap means of suppressing interference with the fuel-level signal due to the vehicle's movement (fuel moving in tank). The system is suitable for all types of fuel tank.