Showing papers on "Digital signal published in 1981"

The maximum sampling rate of digital filters under hardware speed constraints

Abstract: This paper presents a framework for Fiding efficient multiprocessor realizations of digital filters. Based on simple graph-theoretic concepts, a method is derived for determining the minimal sampling period of a given digital filter structure when the speed of arithmetic operations is given but the number of processing units Is unlimited. It Is shown how realistic hardware implementations can be found and evaluated by using the timing diagram of this maximal rate realization as a starting point. The minimal sampling periods of several common digital filter structures are given in terms of addition and multiplication times.

Characteristics of a digital mobile radio channel

Abstract: A field test has been made in order to better understand the digital mobile radio channel. At the mobile receiver (450 MHz, 1200 bits/s) recordings were made of the digital signal and the field strength. These recordings were later analyzed by a computer. Some existing models for digital channels have been tested. Theoretically motivated probability density functions for the fading envelope have also been considered. A new model for the digital channel is proposed. This model is a memoryless binary symmetric channel (BSC) with field strength dependent crossover error probability. This model fits very well to the recorded data.

A New Class of Polyphase Pulse Compression Codes and Techniques

Abstract: A new class of symmetric radar pulse compression polyphase codes is introduced which is compatible with digital signal processing. These codes share many of the useful properties of the Frank polyphase code. In contrast with the Frank code, the new codes are not subject to mainlobe to sidelobe ratio degradation caused by bandlimiting prior to sampling and digital pulse compression. It is shown that bandlimiting the new codes prior to pulse compression acts as a waveform amplitude weighting which has the effect of increasing the mainlobe to sidelobe ratios.

Collision avoiding system and protocol for a two path multiple access digital communications system

Abstract: With the advent of digital communications, it is common to transfer packets of information among a plurality of stations, e.g., digital computers. In order to control the transfer of the packets, various protocols have been introduced. However, the efficiency related to known multiples access digital communications system protocols tends to decrease as the digital signal rate increases. To overcome such problems, the instant communications system and protocol contemplate a communications loop having first and second oppositely directed signal paths. At least two stations are coupled to both the first and the second signal paths. A station includes an arrangement for writing a first signal on the first path and an arrangement for reading a second signal from the second path. In addition, the station includes an arrangement for reading a third signal from the first path. The third signal is coupled from the first path to the station by an arrangement which electrically precedes the arrangement for writing the first signal on the first path. If the station has a packet to transmit, it can overwrite a busy control field of the third signal packet on the first path. Having read the third signal on the first path, a logical interpretation may be made within the station as to whether the first path is busy or not busy. If the first path is not busy, the packet may be written on the first path by overwriting the third signal thereon. If the first path is busy, the station may overwrite a request control field of the third signal for indicating that the station was unable to transmit the packet. The packets flow around the loop and are monitored on the second path. Eventually all packets will be transmitted and the request control field may be detected at the receive side of a head station for indicating the event that all packets have been transmitted, in which event a new cycle may be started by initializing each station on the loop and by permitting each station to transmit.

Systolic Algorithms for Running Order Statistics in Signal and Image Processing

Abstract: Median smoothing, a filtering technique with wide application in digital signal and image processing, involves replacing each sample in a grid with the median of the samples within some local neighborhood. As implemented on conventional computers, this operation is extremely expensive in both computation and communication resources. This paper defines the running order statistics (ROS) problem, a generalization of median smoothing. It then summarizes some of the issues involved in the design of special purpose devices implemented with very large scale integration (VLSI) technology. Finally, it presents algorithms designed for VLSI implementation which solve the ROS problem and are efficient with respect to hardware resources, computation time, and communication bandwidth.

Voice signal converting device

Abstract: A voice signal converting device is adapted for a digital communication network which handles digitized voice signals and data signals simultaneously or equally. A bit for discriminating whether a signal in communication is a voice signal or a data signal is applied in a digital signal channel. The voice signal converting device is connected to a digital communication path to detect the discrimination bit from the incoming signal in such a manner that when a bit group corresponding to the discrimination bit represents the voice signal, the bit group is converted into a predeterminedly correlated bit group and delivered out and when the bit group corresponding to the discrimination bit represents the data signal, this bit group is delivered out in its original form. Consequently, even when the voice signal and the data signal coexist in one communication, speech quality of the voice signal and bit integrity of the data signal can be guaran

Digital in-circuit tester

Abstract: A circuit adapted for use in a high speed computer controlled digital in-circuit tester for obtaining high pulse fidelity at each electrical node of a circuit under test is provided. High pulse fidelity is obtained by minimizing the current in the power supply and digital test signal current loops for the components of the circuit under test. The tester includes a plurality of programmed memory digital test-signal generators responsive to the computer for generating and supplying to the nodes of the circuit under test a complex sequence of digital logic signals. The circuit also includes a plurality of distributed programmable power sources, each power source associated with at least one of said test signal generators, for generating the power supply voltages for the components. The power supply voltages for the components under test are obtained from the programmable power sources associated with the test signal generators involved in generating and supplying the test signals to those components, thereby localizing the component power supply current loops and the driving digital test signal current loops.

Service integrated digital transmission system

Abstract: A service integrated transmission system for transmitting, over a light transmission path, digital signals having a transmission band whose upper limit frequency corresponds to the maximum bit rate of the signals to be transmitted, the transmission being effected by simultaneously transmitting, over the transmission path, digital signals having a high bit rate only in an upper part of the transmission band and digital signals having a low bit rate only in a lower part of the transmission band. The system includes a transmitter at one end of the path which separately multiplexes low bit rate signals into a narrowband signal and high bit rate signals into a broadband signal, combines those multiplexed signals, and modulates a light source with the combined signal. A receiver at the other end of the path converts the modulated light signal into a demodulated electrical signal, separates the two multiplexed signals, and then demultiplexes each of the latter signals.

Electronic humidity control

Abstract: A control system for a humidifier, associated with a hot air furnace, that attains a high level of relative humidity without causing any condensation on the building interior by varying the level of operation of the humidifier as a function of the rate of heat loss from the building. Since the duty cycle of the furnace is a function of the rate of the heat loss, the system generates a digital signal related to the duty cycle and uses that signal to interrogate a digital memory storing a program of desired humidities for various duty cycles to output an instantaneous desired humidity signal which is compared with a measured humidity signal to develop an on/off control signal for the humidifier.

Phase corrected clock signal recovery circuit

Abstract: As shown in Fig. 4 a phase corrected clock signal recovery circuit (150) for multilevel digital signals includes a transition marker generator (200) for generating a narrow width pulse each time a received multilevel digital signal crosses one of the threshold levels between the adjacent logic levels of multilevel signal. Picket fence-like pulse trains are thus formed, the pulses (transition markers) of which correspond to the threshold crossings of the received digital signal. The pulse trains are interspersed with spaces or eye intervals which correspond to the absence of any threshold crossings. Each eye interval additionally corresponds to the time during which each respective bit of digital signal information is transmitted. The rate of occurrence of the pulse trains is substantially equal to the clock frequency of the received digital signal. A phase error detection circuit (400) is operatively coupled to the output of the transition marker generator (200) and to an electronically tune bandpass filter (300) capable of adjusting the phase of the pulse trains. More specifically, the phase error detection circuit (400) includes an up/down counter (410, 411) and adjusts the phase of the clock signal recovered from the pulse trains such that the number of transition markers generated during the high portion of the clock signal equals the number of transition markers generated during the low portion of the clock signal. Thus, selected transitory edges of the pulses of the recovered clock signal are centered at the middles of the respective eye intervals, that is, at the points in time when each respective bit of multilevel digital signal information occurs. This phase corrected recovered clock signal is conveniently applied to appropriate sampling circuitry to enable sampling of the multilevel digital signal at optimum times, that is, at the center of the eye intervals.

Digital control of number of effective rows of two-dimensional charge-transfer imager array

Abstract: Digital control means responsive to an applied digital signal controls which row or rows of an N row-Q column CCD imager are effective in transferring charge and which are not. Such digital control is suitable for use in providing variable gain for a time-delay integration (TDI) charge-transfer imager in accordance with the average brightness level of the light incident on the imager.

A single-chip digital signal processor for telecommunication applications

Abstract: A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.

Amplifier employing digital modulator circuit

Abstract: An amplifier (FIGS. 1-3) is disclosed for amplifying an amplitude and frequency varying input signal. The amplifier includes a circuit (24, 100) responsive to the input signal to provide a digital representation thereof. In addition, a plurality of signal sources (30-36) are provided which each provide an associated signal. Another circuit (38-52) combines selected ones of the associated signals in accordance with the digital representation to provide a first combined signal having substantially the same waveform as, but of greater amplitude than the input signal. In several embodiments, a circuit (74, 76-78) provides an error signal in accordance with the difference between the desired and actual forms of the first signal. This error signal is combined with the first combined signal to derive an error corrected signal.

Digital positioning systems having high accuracy

Abstract: A digital positioning system having high accuracy is disclosed, which employs an incremental position optical encoder as the position transducer. In response to the output signal from the encoder, the system provides coarse and fine position signals which are combined to form a composite digital signal representing the absolute position of a moveable control member. The composite position signal has a resolution of greater than one part in one million. Trigonometric conversion techniques are used to derive high resolution incremental position information from the encoder output signals.

Digital Signal Processing Applications of Systolic Algorithms

Abstract: VLSI structures and algorithms are given for bit-serial FIR filtering, IIR filtering, and convolution. We also present a bit-parallel FIR filter design. The structures are highly regular, programmable, and area-efficient. In fact, we will show that most are within log factors of asymptotic optimality. These structures are completely pipelined; that is, the throughput rate (bits/second) is independent of both word size and filter length. This is to be contrasted with algorithms designed and implemented in terms of, say, multipliers and adders whose throughput rates may depend on word length.

Suppression of limit cycles in digital filters designed with one magnitude-truncation quantizer

Abstract: A sufficient condition for the absence of zero-input granularity limit cycles in error feedback digital filters designed with one magnitude-truncation quntizer is presented. This sufficient condition Is satisfied, i.e., no limit cycles can exist, in first- and second-order digital filters, if the parameters in the error feedback loop are properly chosen. The roundoff noise in these digital filters is also discussed.

Control information communication method and system through a common signal transmission line

Abstract: Transmission and communication of control information through a common signal transmission line are performed with a high transmission efficiency by the use of a control data signal including a content code signal portion and a sub-data signal portion but no address signal portion. The content code signal portion and the sub-data signal portion are representative of a brief content and a supplemental content of control forming in combination control data in the control data signal, respectively. A station with which an equipment is connected and which is coupled with the common transmission line contains at least one content code data so that when the content code signal portion of the control data signal is concurrent with one of the at least one content code data the equipment takes the control data signal for performing the control defined by the control data formed by content code and the sub-data signal portions of the received signal. The equipment is also capable of transmitting a control data signal similar to the above-mentioned one to the common transmission line.

Waveform synthesis using multiplexed parallel synthesizers

Abstract: A novel signal synthesizer provides high frequency synthesized waveforms for the user. By converting phase information into digital outputs in parallel and by selectively coupling these digital outputs, an ordered digital output is formed to provide the high frequency waveforms. This ordered digital output, which represents points on a sine function, is converted to an analog signal for the synthesizer output. Furthermore, frequency and phase modulations of the synthesized waveforms are easily implemented with this novel signal synthesizer; the modulation information is simply added to the digital outputs prior to selectively coupling. Thus when the ordered digital output is converted to an analog signal, the analog signal contains the modulation information.

Phase tolerant bit synchronizer for digital signals

Abstract: A bit synchronizer for digital data signals capable of tracking phase errors of up to ±180° without loss of lock. An input data signal is squared and then applied to a pair of D-type flip-flops. The flip-flops are alternately driven by a clock signal generated by a voltage controlled oscillator in a phase-locked loop. The flip-flops cause the input data to be shifted 0° and 180°, respectively, with reference to the clock signal. The flip-flops are cross-coupled to a pair of exclusive-OR gates, in a manner such that as the phase error between the input signal and the clock signal increases or decreases, the pulse width out of one gate varies proportionately while the output of the other gate is a pulse which is always one-half the clock signal period. The phase relationship of the pulses out of the gates switch 180° as the phase error traverses the 0° point. The outputs of the gates are summed to provide a measure of the phase error between the clock signal and the input signal and to produce a net control voltage representative thereof. The control voltage is applied to the oscillator to cause the frequency and phase of the clock signal generated thereby to be synchronous with that of the input signal. In the absence of bit transitions, the phase-locked loop is biased to seek the tuned bit rate. The described arrangement permits tracking phase errors over a ±180° range without loss of synchronization.

Broken drill bit detector

Abstract: A Drill Bit detector for use with numerically controlled drilling machine capable of sensing missing or broken Drill Bits in the range of 1 mil to 30 mils in diameter, or larger, is described. An infrared emitting diode is driven at a predetermined frequency with the pulsed light being directed through fiber optic cable directed at a portion of the Drill Bit to be detected. A change of light intensity occurring when a Drill Bit is missing is detected and the pulsed light detected converted to a pulsating electrical signal at the input frequency of the pulse light source. A frequency responsive circuit converts the pulsating electrical circuit to a digital signal indicative of the absence of the sensed Drill Bit. A timer determines whether or not the sensed digital signal occurs for a predetermined threshold time period, and causes it to be ignored as spurious if less than the predetermined time interval, or causes the drilling machine operation to be halted if occurring longer than the threshold time period. Multiple detection circuits are illustrated for use with most multiple drill spindles.

NRZ Digital data recovery

Abstract: The clock signal required for demodulation of a received NRZ digital data stream is generated by detecting each transition across a reference axis made by the received NRZ digital data stream. This transition data is then utilized to change the voltage applied to a voltage controlled oscillator. The change in the voltage applied to the voltage controlled oscillator causes the frequency of the output from the voltage controlled oscillator to change. The change in the frequency of the output of the voltage controlled oscillator adjusts the period of the clock signal until the clock signal is synchronized with the transition data at which time it may be used to demodulate the recieved NRZ digital data.

Scan signal processing system

Abstract: An analog scan signal having a repetitive background waveform is converted into a multi-level signal through a peek hold circuit, a converter, a digital memory and a discriminator. The peak hold circuit detects and holds the peak voltage of the current scan lines. The background waveform is normalized by the peak voltage and converted into a digital signal in the converter and stored in the memory. The analog scan signal is discriminated in the discriminator on the basis of a reference voltage produced with the normalized background waveform read out of the memory and converted in the converter and with the current peak voltage supplied from the peak hold circuit.

Method and device for detecting, recording and evaluating physical measurement data

Abstract: A sensor (1) for detecting measurement values of physical quantities is connected via a sensor line (2) to a mobile data receiving unit (3) in which the analog electrical signal supplied by the sensor (1) is converted by an analog/digital converter (4) into a storable digital signal (21). A time-clocked (5) logic circuit (6) contains switching means for transferring digital measurement value signals which are present into the measurement value memory (7a) of a memory unit (7) existing in the data receiving unit (3). Characteristic data of the sensor (1) which is in each case connected to the data receiving unit can be digitally stored in a characteristic-data memory (7B) also contained in this memory unit. The sensor (1) and the data receiving unit (3) are designed in such a manner that measurement values detected by the sensor (1) over a certain period are recorded so that they can be called up independently of additional external aids. For this purpose, the data receiving unit is connected via a stationary adaptor (10) to an also stationary evaluating unit (11), for example an EDP system, and/or analog recording means, the data receiving unit (3) being temporarily connected to the adaptor (10) via a multiple connector (9, 9'). The adaptor contains switching means for the direct or indirect inputting of recording variables for conditioning and storing the measurement values determined, means for calling up the measurement value and characteristic data stored in the memory unit (7) of the data receiving unit (3), and means for conditioning and supplying the data called up from the data receiving unit for the purpose of evaluation of these data in the evaluating unit (11).

Application of a Digital Signal Analyzer to the easurementTofF Power System Ground Impedances

Abstract: A new method is described for measuring the impedance of power system ground systems where, because of a significant reactive component or the presence of a large residual power system voltage, conventional ground resistance measuring instruments cannot be used. A white noise source together with a digital signal analyzer are used. Results of three applications are given.

Analogue to digital signal conversion and storage system

Abstract: In an analogue to digital converter, the analogue signal applied thereto is sampled at successive time intervals and at each sample a digital signal is produced and the time interval between successive samples is not necessarily constant but is dependent upon the rate of change of amplitude of the analogue signal during said time interval. The digital signals may be applied to a counter to produce data representative of the time interval between successive samples and also to indicate whether the analogue signal has increased or decreased between successive samples. This data may then be recorded in a manner to provide substantially constant recording density.

Signal processing for digital optical disc players

Abstract: The dc coupled signal processor of the invention provides a method for accurately converting an analog input signal from a digital optical disc which signal has a finite rise time to a digital signal with accurately positioned edges by preserving the dc content of the input signal. A peak-to-peak detector detects the average of the peak-to-peak analog signals and feeds it to a low pass filter which operate above the periodic drift-like analog input signal. The output of this filter is employed as a reference voltage by a comparator which is used as a slicer or zero crossing detector. The comparator output is a digital signal with minimum bias distortion. The output of the filter is also fed to a differential amplifier and a second low pass filter which operates at a frequency below the cutoff of the periodic drift analog input signal. The resulting signal is negatively fed back to the input to be summed and amplified with the input analog signal.

Line protocol for communication system

Abstract: In a communication system, a line protocol format with a variable bit rate and low bit overhead provides for the high integrity, synchronous exchange of digital signal information between master and slave processing units, with master processing unit controlling the line protocol.