Showing papers on "Digital signal published in 1985"

Multirate digital signal processing

Abstract: There has been a great deal of material in the area of discrete-time transforms that has been published in recent years. This book does an excellent job of presenting important aspects of such material in a clear manner. The book has 11 chapters and a very useful appendix. Seven of these chapters are essentially devoted to the Fourier series/transform, discrete Fourier transform, fast Fourier transform (FFT), and applications of the FFT in the area of spectral estimation. Chapters 8 through 10 deal with many other discrete-time transforms and algorithms to compute them. Of these transforms, the KarhunenLoeve, the discrete cosine, and the Walsh-Hadamard transform are perhaps the most well-known. A lucid discussion of number theoretic transforms i5 presented in Chapter 11. This reviewer feels that the authors have done a fine job of compiling the pertinent material and presenting it in a concise and clear manner. There are a number of problems at the end of each chapter, an appreciable number of which are challenging. The authors have included a comprehensive set of references at the end of the book. In brief, this book is a valuable contribution to the general areas of signal processing and communications. It can be used for a graduate level course in perhaps two ways. One would be to cover the first seven chapters in great detail. The other would be to cover the whole book by focussing on different topics in a selective manner. This book by Elliott and Rao is extremely useful to researchers/engineers who are working in the areas of signal processing and communications. It i s also an excellent reference book, and hence a valuable addition to one’s library

Fast Algorithms for Digital Signal Processing

Abstract: Fast algorithms for digital signal processing , Fast algorithms for digital signal processing , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Analog and digital telemetry system for an implantable device

Abstract: In an implantable device, transmission and reception of digital information is accomplished as well as the transmission and reception of analog information. The analog signal is FM modulated for transmission and the digital signal is phase modulated for transmission. The FM modulated signal is used as a clock in the phase encoding of the digital signal and thus provides a signal simultaneously carrying analog and digital information. Means for reception of the analog and digital information is taught. The use of PSK (phase shift keying) as the phase modulation scheme for transmission and reception is also taught.

Personal electrocardiogram monitor

Abstract: A pocket-sized, self-contained electrocardiogram monitor with a dot-matrix, liquid-crystal display. The monitor uses dry electrodes and is suitable for direct placement against the patient's chest without the use of paste or gel to insure electrical contact. An A/D converter converts an ECG signal to a digital signal which is then processed by a microprocessor and then displayed on the liquid-crystal display in real time. The microprocessor is programmed to select the maximum and minimum digital values from four consecutive samples from the A/D converter and to supply data representative of the maximum and minimum values to the display at one-fourth the conversion sampling rate.

Aircraft flight data recorder data acquisition system

Abstract: A data acquisition system (18) for use in an aircraft flight data recorder (10) receives multiple analog (12) and discrete signals (14) representative of various aircraft parameters. A single address command from the fligth data recorder (10) central processing unit (CPU) (24) causes a first multiplexer (56) to select a set of analog signals. Each selected analog signal is amplified (61, 62, 63) by a gain factor under CPU (24) control and passed to track-and-hold circuitry (71, 72, 73) which holds a level of the amplified analog signal upon receipt of a suitable command. The held analog signal levels are passed to a second multiplexer (80) which also receives a set of discrete signals selected by a third multiplexer (84) in response to a CPU (24) address command. A control sequencer (96) sequentially passes each signal at the input of the second multiplexer (80) through an analog-to-digital converter (90) with the resultant digital signal being loaded into memory (92). After either all the selected and processed analog signals or the selected discrete signals have been analog-to-digital converted and stored in memory, the control sequencer (96) issues an interrupt signal to the CPU (24).

Apparatus for automatically inspecting objects and identifying or recognizing known and unknown portions thereof, including defects and the like and method

Abstract: Apparatus and method for automatically inspecting objects and identifying or recognizing known and unknown portions thereof, including defects and the like, involving storing digital signal information representing an image of the desired predetermined object shapes to be learned by an image inspecting system and recognized during scanning of objects to be inspected, and modifying the stored digital signal information to create a fictitious image of the object shapes to be learned that incorporates acceptable size or dimension variations and the like in such objects such that during the inspecting of future objects, these acceptable variations will be ignored as defects or unknown elements.

Digital signal transmitting system

Abstract: PURPOSE:To make connection between devices simple, simplify circuit configuration and make the device small and light by transmitting digital signals using three signal lines, i.e. a data transmission request signal line, a data signal line and a clock transmitting line. CONSTITUTION:A data transmission request signal line 3 is connected from an output port P03 of a microprocessing device 15 in a device 2 to a device 1 through a protective resistance r3. In the device 1, the signal is sent to an input port Pi1 of a processing device 11 through a protective resistance r1. On the other hand, a data transmitting line 4 transmits two-way signals between the devices 1 and 2. For instance, when a signal is sent from the device 1 to 2, the signal is connected from an output port P01 to the device 2 through an open collector driver 12. In a clock transmission signal line 5, clock outputted from an output port P02 of the device 11 of the device 1 is connected to the device 2 through an open collector driver 13, and connected to an input port Pi3 of a device 15 through a pull-up resistance R3 and a protective resistance R5.

A unified approach to orthogonal digital filters and wave digital filters, based on LBR two-pair extraction

Abstract: The LBR-extraction approach is extended in order to derive wave digital filters and several orthogonal digital filters in a unified manner. The derivation clearly places in evidence the underlying orthogonality property of all these structures, which can therefore be implemented based on a simple building block, namely, the "planar rotation" operator. The derivation directly emphasizes the concept of "structural boundedness" as a requirement for low sensitivity. In addition to wave and orthogonal filters, a number of other methods for forcing structural boundedness are indicated.

Code converting system and method for band compression of digital signals

Abstract: A code converting system for converting a digital signal having a given number of bits into a digital signal having a different number of bits, which selectively alters the encoding method depending on the nature of the input to the system. The system includes a variable length encoder; a run-length encoder; a multiplexer for selecting as its output either the variable length code or the run-length code; a buffer memory for receiving and storing the output of the multiplexer, supplying it to a transmission line, and generating a signal indicative of the level of memory occupancy of the buffer memory; and control means for controlling the multiplexer so as to output only variable length code when the memory occupancy is below a first predetermined level. The control means further comprises an underflow signal generator for generating a signal indicative of when the memory occupancy is less than the first predetermined level. The underflow signal is supplied to a gate, which transfers it as a selection signal to control the multiplexer so as to output only said variable length code when such underflow occurs. In the absence of an underflow indication signal, the gate is enabled to pass the input code, to the run-length encoder to be converted into a run-length code. The control means is also adjustable so as to control the level of memory occupancy of the buffer memory.

Predictive communication system filtering arrangement

Abstract: A digital communication system includes a predictive decoder (30) that is operative to convert received digital codes into a predictively decoded signal, e.g., speech signal, and to generate a set of predictive parameter signals and a signal representative of the communication system bit rate. A set of filter control signals is generated (325) responsive to the communication bit rate signal. The predictively decoded signal is passed through a filter (335) which modifies the output signal responsive to the filter control signals and the decoder predictive parameter signals to improve the output signal quality. The filter control signals selectively alter the predictive parameter signals to optimize the predictively decoded signal modification for the current transmission bit rate.

Digital phase-locked loop and frequency measuring device

Abstract: Method and apparatus are disclosed for providing a sampling signal having a frequency which is maintained in constant proportion to the frequency of an input signal. The input signal is sampled at instants determined by the sampling signal to provide a plurality of data signals associated with one cycle of the input signal. A signal processor is adapted to receive first and second pluralities of data signals associated with first and second cycles of the input signal and to perform two discrete Fourier analyses to provide two phasor signals representing two voltage phasors of respective fundamental frequencies of the discrete Fourier transforms. The phasor signals are used to generate a difference signal indicative of the angle between the two voltage phasors and, therefore, proportional to the difference between the sampling frequency and the input frequency. The difference signal is used to modulate the period of the sampling signal such that the frequency of the sampling signal is maintained in constant proportion to that of the input signal.

Solid state image sensor

Abstract: A solid state image sensor comprising a plurality of photosensors (8A) including a plurality of avalanche photodiodes (12A) arranged at least in the form of a one-dimensional array and delivering pulse signals each representing the number of photons incident to each of the photosensors; counters (10A) connected to the respective photosensors (8A) to count the pulse signals and hold the count value as a video output; a reset circuit (5) for resetting the counters (10A) to the initial states at a predetermined frequency; and a scanning circuit (14) for sequentially reading out the count value in the counters (10A). The counter (10A) counts the number of photons subjected to photoelectric conversion by the photodiode (12A) so that the video signal is directly derived in the form of a digital signal and thus the video signal with a high S/N ratio is obtained.

Digital PBX integrated workstation security system

Abstract: A theft alarm system for use in combination with a digital signal PBX telephone system, includes a plurality of electronic tethers connected to individual pieces of protected equipment. Removal of the tether is automatically detected by a local security monitor which reports the condition to a central security controller via the PBX system. The security controller then provides dial-up reporting of the theft and/or sets an audible alarm at the equipment site.

Digital frequency modulator

Abstract: An MSK modulator includes a source of digital sawtooth signals having a recurrence rate equal to the desired recurrence rate of the unmodulated carrier. The digital sawtooth signal is applied to an adder together with a phase control digital signal. The phase control digital signal phase-shifts the digital sawtooth signal. The phase-shifted digital sawtooth signal is applied to a sine ROM to produce a digital sinusoid with an unmodulated recurrence rate equal to the recurrent rate of the digital sawtooth signal. When the phase control signal is an accumulated signal, the digital sinusoid is frequency-modulated. The phase control signal for MSK modulation is a ramp signal generated by a controlled accumulator. The accumulator includes a controllable clocked adder/subtractor, the output of which is coupled by way of a register back to an input. The other input of the adder/subtractor is coupled to receive a fixed ramp rate controlling word. At each clock cycle, the accumulator adds (subtracts) the ramp rate word from the sum under the control of the MARK (SPACE) information content of the information signal to form a two-frequency MSK modulation. More general frequency modulation is accomplished by an accumulator with an input word which responds to the instantaneous amplitude of the information signal. A clocked delay and a subtractor indicate the direction of frequency deviation.

Multi-level decision circuit

Abstract: An input multi-level amplitude sgnal of 2M levels is supplied via a DC level controller (12) to an AD converter (14) for conversion into an N-bit (N being an integer greater than M) digital signal, and M high-order bits of the digital signal are provided as decided outputs. it is decided by a decision means (29) whether a deviation of the DC level of the multi-level amplitude signal at the input side of the AD converter is in excess of a predetermined value. When the deviation of the DC level is decided less than the predetermined value, the outputs of bits less significant that the Mth bit in the digital signal are integrated for input as a DC level control signal into the DC level controller, correcting the deviation of the DC level. When it is decided by the decision means that the deviation of the DC level is greater than the predetermined value, at least one of the M high-order bit outputs in the output digital signal is integrated for input as a DC level control signal into the DC level controller, correcting the deviations of the DC level.

Metal detector having digital signal processing

Abstract: A metal detector circuit includes a transmit coil (12) and a receive coil (56) arranged in a balanced induction configuration in an electromagnetic field. The receive signal from the receive coil (56) is input to electronic switches (146, 148) which receive quadrature reference inputs from a phase shift circuit (112). The phase demodulated outputs of the switches (146, 148) are passed through amplifiers and input to an analog-to-digital converter (324) to produce digital signal samples which are transmitted through a bus (326). The bus (326) is connected to random access memory (414, 416) and a read only memory (418) which includes a stored signal processing program. A microprocessor (374) is connected to the bus (376) for receiving the digital signal samples and the stored program from memory (418). The microprocessor (374) executes the stored signal processing program to produce a digital output signal which is transmitted through the bus (326) to a digital-to-analog converter (360). The converter (360) produces an analog output signal which is passed to an output driver circuit which produces a target indication signal at a speaker (284). The digital signal processing provided by the microprocessor (374) includes concurrent ground cancellation and discrimination without the need for operator selection of these functions. The digital output produced by the microprocessor (374), upon detection of an object in the electromagnetic field, can be displayed in digital readouts (474-482).

Digital signal delay circuit

Abstract: A digital signal delay circuit which delays a plurality of digital input signals by a use of a single delay device group and a plurality of delay sections is disclosed. The delay device group generates a plurality of different phase clock signals. Each of the delay sections includes selection means for selecting one of the clock signals from the delay device group and latch means for latching the digital input signal in response to the output signal from the selection means. The output signal from the latch means is the delayed input signal, and a delay time is controlled by the selection means. The delay device group is used in common for the plurality of delay sections, so that the digital signal delay circuit is simple and inexpensive in construction.

Suppressed clock pulse-duration modulator for direct sequence spread spectrum transmission systems

Abstract: In the disclosed digital circuit, a digital direct sequence modulation signal is converted to a suppressed clock pulse-duration modulation signal to thereby suppress the clock feature in the frequency spectra of a spread spectrum transmission system. The disclosed digital circuit includes a parallel output shift register for converting the direct sequence modulation signal to a corresponding series of four-bit digital words. The digital words supplied by the shift register are loaded into a four-bit synchronous binary counter circuit. The counter circuit counts upwardly from the value of the digital word and supplies a carry pulse to a logic circuit which, in turn, produces an output pulse, the duration of which is representative of value of the digital word supplied by the shift register. The pulse-duration modulation signal supplied by the logic circuit is modulo-2 added with a signal having one-half the clock rate of the information embedded in the direct sequence modulation signal to supply the suppressed clock pulse-duration modulation signal.

Digital linear actuator

Abstract: A digital linear actuator includes a plurality of digital actuator cells each connected to the next in sequential fashion. Each of the digital actuator cells contracts or expands a predetermined amount along an expansion/contraction axis when it is actuated by a corresponding digital signal. Each digital actuator cell includes an inner portion containing a medium which expands or contracts in response to a digital signal. The inner portion is disposed within an outer portion that contracts in the direction of the axis in response to expansion of the inner portion, and expands in the direction of the axis in response to contraction of the inner portion. The device is useful in simulating the behavior of a muscle in a prosthetic device. Several embodiments of the invention are disclosed in which an arm can be extended to and retracted from a snake-like configuration. Another embodiment of the invention is disclosed which effectively simulates a shoulder and arm mechanism.

Information signal delay system utilizing random access memory

Abstract: An information signal delay system utilizes a solid-state memory for continuously storing the information and reading it out on a time-delayed basis. An information signal is converted into a digital format and compressed using conventional compression algorithms. The compressed digital signal is then sequentially written into successive locations in a random access memory. These locations are sequentially addressed at a later point in time to read the digitized information out of the memory on a time-delayed basis relative to when it was stored in the memory. The time delay is related to the anticipated reaction time it takes to cycle completely through all of the address locations in that portion of the memory being used to store the information. The digitized information that is read out of the memory can be synthesized or otherwise suitably processed to reconstruct the original information signal as a delayed signal.

Method and apparatus for performing pattern recognition analysis

Abstract: A method and apparatus for performing pattern analysis of a digital signal containing at least one waveform, detects a fiducial point of each waveform of the digital signal; captures slope transition features separated by interval features of each of the waveforms of the digital signal; creates a signature for each waveform based on the captured slope transition and interval features of each of said waveforms; determines the closest proximity of the signature to one of a plurality of previously determined classifications of signatures; creates a new classification with the signature if the closest proximity has a value less than a predetermined threshold value; and adds the signature to the closest classification if the closest proximity has a value at least equal to the predetermined threshold value.

Random array sensing devices

Abstract: A sensing device for generating an output signal corresponding to an input signal which comprises a substrate, an array of sensor elements for receiving the input signal and transfer members located on the surface of the substrate and interposed between the sensor elements. The sensor elements have their barycenters distributed on the surface of the substrate in a random non-periodic pattern. The transfer members are coupled to the sensor elements and generate the output signal. The sensing device is incorporated in an apparatus which generates an output signal from an input image wherein the output signal is substantially free of detectable aliases. The apparatus includes an image pick-up device for viewing the input image and transmitting radiation to the image sensing device, an analog-to-digital converter for converting the analog signal from a sensing device to a digital signal, a position encoder, an interpolator and a memory means for storing the output of the interpolator. The position encoder is provided with a plurality of storage addresses for storing digital signals each having a value corresponding to the intensity of the radiation incident on a corresponding sensor element, and the interpolator generates a plurality of signals corresponding to intensity values intermediate to those stored in the storage addresses of the position encoder.

Root fracture and the design of prefabricated posts.

Abstract: The derived signal is then converted to an analog signal for x-y recording and a digital signal for readout. A chart recorder takes the analog signal and displays it in an x-y format where the ordinate is torque (calibrated in inch-ounces) and the abscissa is angular rotation. The angular signal is developed from a five-turn precision potentiometer geared to the output rotor of the transducer (Fig. 1). Calibration of the system was accomplished according to the manufacturer’s procedure followed by application of a known fixed torque to a calibrated weight and beam. A correction of +3 inch-ounces was added to the measured readings as a calibration factor. The system was designed to generate a maximum torque of 200 inch-ounces; that magnitude was not exceeded during the experiment. Fig. 2. Resin, Silastic membrane, and tooth block in place in the XYZ movable fixture.

A 3-/spl mu/m CMOS Digital Codec with Programmable Echo Cancellation and Gain Setting

Abstract: A 3-/spl mu/m CMOS digital signal processor (DSP) performs speech signal shaping, programmable echo cancellation and gain setting functions for telephone applications. A/D and D/A conversions are performed by making use of /spl Sigma//Spl Delta/ modulators, decimator, and interpolator filter blocks. In addition, the DSP acts as a control interface between the subscriber line interface circuit (SLIC) and the line card controller, the denouncing of eight line status bits included.

A multiprocessor architecture for two-dimensional digital filters (computer, signal, processing, image, parallel)

Abstract: Multiplication, addition and data transfer are the primary operations required for digital filtering. It is important to minimize data communication requirements (data transfer) as well as exploit inherent parallelism for algorithms in order to implement them in real-time with the use of a multiprocessor system. This research is oriented toward the development of a computationally efficient algorithm for digital filtering. A state-space representation is derived for general order one-dimensional and two-dimensional digital filters. An algorithm is then developed from this representation. This algorithm not only exposes the inherent parallelism for these filters but also reduces data communications requirements. A software package for spatial domain IIR digital filters has been implemented on VAX-11/780. This software package is based upon the state-space representation and was used to filter various images to test the performance of the algorithm. A new generic computational primitive is introduced for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. A computational structure based upon this primitive has very high efficiency and very low data transfer and storage requirements. It can form the basis for a programmable special purpose chip for digital signal and image processing applications. A new multiprocessor architecture for real-time image processing is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme and a simple interconnection network. Thus, it avoids the bottleneck associated with traditional parallel computers and multiprocessor systems.