Showing papers on "Digital signal published in 1987"

Implementing the Rivest Shamir and Adleman public key encryption algorithm on a standard digital signal processor

Abstract: A description of the techniques employed at Oxford University to obtain a high speed implementation of the RSA encryption algorithm on an "off-the-shelf" digital signal processing chip. Using these techniques a two and a half second (average) encrypt time (for 512 bit exponent and modulus) was achieved on a first generation DSP (The Texas Instruments TMS 32010) and times below one second are achievable on second generation parts. Furthermore the techniques of algorithm development employed lead to a provably correct implementation.

Digital signal processor and processing method for GPS receivers

Abstract: A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P 1 , and P 2 channels on the L 1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

Satellite communications system for medical related images

Abstract: A satellite communications system for transmitting medical related images from a mobile unit to a central headquarters and then sending back diagnostic analysis from the central headquarters to the mobile unit by having a high resolution camera and a video compressor for converting high resolution images into voltage analog signals, a modulator for converting the voltage analog signals into a narrow band width and low frequency signal, a satellite system for transmitting and receiving images and analyses, a demodulator for converting the narrow band width and low frequency signal back into a voltage analog signal, a video expander for converting the voltage analog signal into a digital signal, a buffer for buffering the digital signal, a high resolution monitor for converting the buffered digital signal into a high resolution digitized image.

Method of digital sound broadcasting in television channels with spectrum interlacing

Abstract: Digital broadcasting of a sound program takes place in a channel of a set of channels. In each channel other than that dedicated to digital broadcasting, the television channel has a spectrum of spectral lines separated by low spectral power density intervals. Digital broadcast is achieved by digital modulation (for instance OFDM) of the transmission with frequency multiplexing using a spectrum interlaced with that of the television. The digital signal is recovered by comb filtering on reception.

Digital zero IF selectivity section

Abstract: A digital zero-IF selectivity section circuit which operates on a recovered input signal (12), digitally clocked by a first clock (22) at a rate of FS, in receiver device. The circuit uses a second clock (24) operating at a lesser rate than the first clock (22) to clock an N-order FIR digital filtering means (16) to selectively band-limit the frequency spectrum of the recovered input signal (12). A second digital filtering means (20, 28) is coupled to the output of the first FIR digital filtering means (16). The second digital filtering means (20, 28) operates at a clock speed less than or equal to the second clock speed. The second digital filtering means (20, 28) is used to further selectively band-limit the frequency spectrum of the recovered input signal (12).

Digital Communication Systems

Abstract: DIGITAL COMMUNICATION ADVANTAGES AND DISADVANTAGES TOTALECER. INTRODUCTION TO DIGITAL COMMUNICATIONS DIGITAL. INTRODUCTION TO EECS II DIGITAL COMMUNICATION SYSTEMS. PRINCIPLES OF DIGITAL COMMUNICATION SHARIF UNIVERSITY OF. SIMON S HAYKIN DIGITAL COMMUNICATION SYSTEMS WILEY 2013. DIGITAL COMMUNICATION SYSTEMS. DIGITAL COMMUNICATION SYSTEMS NPTEL. DIGITAL COMMUNICATION SYSTEM MODULATION BANDWIDTH. DIGITAL COMMUNICATION SYSTEMS FREE EBOOKS DOWNLOAD. COMMUNICATION SYSTEMS ANALOG VS DIGITAL WIKIBOOKS OPEN. DIGITAL COMMUNICATION SYSTEMS WILEY COM. COMMUNICATION SYSTEMS II. DIGITAL COMMUNICATION DEFINITION OF DIGITAL. MODERN DIGITAL AND ANALOG COMMUNICATION THE AMAZON COM. DIGITAL COMMUNICATION SYSTEMS MCQ SERIES. DIGITAL COMMUNICATIONS FUNDAMENTALS AND APPLICATIONS. DIGITAL COMMUNICATION SYSTEMS 1ST EDITION AMAZON COM. DIGITAL COMMUNICATIONS SYSTEMS MASTER’S DEGREE. DIGITAL COMMUNICATION SYSTEM SLIDESHARE. DIGITAL COMMUNICATION SYSTEMS GOOGLE BOOKS. ANALOG AND DIGITAL COMMUNICATION SYSTEMS BY MARTIN S RODEN. WILEY DIGITAL COMMUNICATION SYSTEMS 1ST EDITION SIMON. DIGITAL COMMUNICATION SYSTEM MANAGEMENT STUDY GUIDE. DIGITAL MODULATION IN COMMUNICATIONS SYSTEMS – AN INTRODUCTION. DATA TRANSMISSION WIKIPEDIA. DIGITAL COMMUNICATION SYSTEMS EBOOK BY SIMON HAYKIN. DESIGN OF A DIGITAL COMMUNICATION SYSTEM SIGNAL PROCESSING. DIGITAL COMMUNICATIONS J S CHITODE GOOGLE BOOKS. INTRODUCTIONTOCOMMUNICATIONSYSTEMS UC SANTA BARBARA. INTRODUCTION TO DIGITAL COMMUNICATION MIT OPENCOURSEWARE. INTRODUCTION TO DIGITAL COMMUNICATIONS SYSTEM. DCSL DIGITAL COMMUNICATION SYSTEMS LIMITED. TYPES OF DIGITAL COMMUNICATION TECHWALLA COM. TELECOMMUNICATION WIKIPEDIA. DIGITAL COMMUNICATION SYSTEMS UNIVERSITY OF OTTAWA. DIGITAL COMMUNICATION BY SIMON HAYKIN PDF 4ED TOTALECER. FUNDAMENTALS OF DIGITAL COMMUNICATIONS SYSTEMS 1 1. COMMUNICATION SYSTEMS ADVANTAGES OF DIGITAL TRANSMISSION. 3 INTRODUCTION TO DIGITAL COMMUNICATION SYSTEMS YOUTUBE. DIGITAL COMMUNICATION SYSTEMS SLIDESHARE. THEORY AND DESIGN OF DIGITAL COMMUNICATION SYSTEMS. ELEMENTS OF A DIGITAL COMMUNICATION SYSTEM. DIGITAL COMMUNICATION SYSTEMS UOTECHNOLOGY EDU IQ. ELEMENTS OF DIGITAL COMMUNICATION SYSTEMS. DIGITAL AND ANALOG COMMUNICATION SYSTEMS. DIGITAL AMP ANALOG COMMUNICATION SYSTEMS 8TH EDITION PDF. DIGITAL COMMUNICATION SYSTEM QUESTIONS AND ANSWERS. DIGITAL COMMUNICATIONS TRAINING SYSTEMS LAB VOLT. DIGITAL COMMUNICATION TUTORIAL. EE2EE2 4 COMMUNICATION SYSTEMS4 COMMUNICATION SYSTEMS

Sample rate conversion system having interpolation function

Abstract: A first digital data processing system outputs digital data obtained by sampling, in response to a clock signal of a first frequency, original data having a characteristic enabling interpolation thereof. A second digital data processing system obtaines output data by sampling input data in response to a clock signal of a second frequency. A sample rate conversion circuit receives the digital data from the first digital data processing system, converts the sample rate thereof into a sample rate suitable for the second digital data processing system, and supplies the sample rate as the input data to the second digital data processing system. The sample rate conversion circuit includes an interpolation circuit for performing interpolation of two adjacent units of data of the digital data received from the first digital data processing system, and an interpolation coefficient calculation circuit for calculating an interpolation coefficient, which is subsequently supplied to the interpolation circuit in accordance with a phase relationship between the clock signals of the first and second frequencies.

Digital direct sequence spread spectrum receiver

Abstract: A direct sequence spread spectrum receiver for receiving an RF carrier radio signal modulated with a message signal in accordance with a code having a fundamental frequency converts the received signal to an IF signal centered about a frequency f o corresponding to the code fundamental frequency offset by a Doppler shift. The IF signal is digitized and sampled at a local clock frequency to develop N-bit digital signals. Locally generated digital phase shifted sine and cosine signals at frequency f o are multiplied by a local code to obtain local 1-bit IF signals which are then correlated with the digitized IF signals to develop in phase and quadrature component signals. A tracker uses the component signals to translate the frequency of the digital local IF signal to track the Doppler shift, to maintain the local sampling frequency at 4f o , and to maintain the local code generator in synchrony with the code of the received signal. Except for the IF down conversion, the receiver employs all digital circuitry. The receiver architecture is adapted to a low power sequential tracking microreceiver.

Programmable array logic cell

Abstract: A programmable array logic cell (60) including a sum-of- products array having a single OR gate (70) for providing a sum signal, and including an XOR gate (80) for combining the sum signal with a product signal provided by an AND gate (78) from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Portable pump for infusing medicine into a living body

Abstract: A portable infusion pump for delivering medicine to a living body has a roller pump for infusing solutions by use of a motor, a driving circuit for driving the motor in response to a control signal, and a flow rate control for generating the control signal. The flow rate control includes a manual operating unit for manually setting a value of a speed of the motor, a speed setting unit for generating a digital signal associated with the value set by the manual operating unit, and a control signal output unit for generating the control signal associated with the digital signal delivered from the speed setting unit. Accordingly, the flow rate thus set clearly corresponds to an actual flow rate, thus facilitating the control of the liquid flow rate.

Bar code scanner and method

Abstract: A scanner for scanning bar code labels and for providing data related thereto to a host computer includes a scanning apparatus for optically scanning bar code labels and for providing an electrical signal in response thereto, and a decoding circuit, responsive to the scanning apparatus for translating the electrical signal into a digital signal. A microprocessor, responsive to the decoding circuit, controls operation of the scanner and translates the digital signal into data to be provided to the associated host computer under control of control characters. The scanner further includes a non-volatile random access control memory in which control characters are stored, and an interface, connected to the host computer and to the microprocessor, for transferring data from the microprocessor to the host computer and for transferring control characters from the host computer to non-volatile random access control memory via the microprocessor.

Method and apparatus for constant density recording

Abstract: Method and apparatus for providing constant density recording is described. A single set of reconfigurable electronics is employed to control the write frequency for a plurality of frequency zones on a magnetic storage disk. The reconfigurable electronics include means for selectively switching a frequency response determining element within a common channel. Switching is controlled by a digital signal provided by a disk file control microprocessor, avoiding the necessity of mechanical linkages and/or changes in spindle rotation rate. The plurality of zones need not be of equal radius in width but the recording frequency within each zone is fixed throughout that zone. Zone selection is under the control of a disk file control microprocessor which produces a digital code to appropriately configure the electronics for the particular zone. Zone switching is done only when a seek across a zone boundary occurs so that no access time penalties result.

Bar code scanner and method of programming

Abstract: The scanner includes scanning circuitry for optically scanning bar code labels and providing an electrical signal in response thereto, decoding circuitry, responsive to the scanning circuitry for translating the electrical signal into a digital signal, and a microprocessor, responsive to the decoding circuitry, for controlling operation of the scanner and for translating the digital signal into data to be provided to the associated host computer under control of control characters. A non-volatile random access control memory is provided for storing control characters. Interface circuitry, connected to the host computer and to the microprocessor, transfers data from the microprocessor to the host computer. A switch enables the microprocessor to translate the digital signal into control characters and enables the microprocessor to store the control characters in the non-volatile random access control memory. The control characters may be character sets which when read by the scanner indicate that two bar code labels are associated with the same item.

Audio digital/analog encoding and decoding

Abstract: Apparatus and an associated method are described for encoding an analog signal to a digital representation thereof and then decoding the same to reconstruct the original analog signal with reduced quantization noise and error. The analog signal is first adaptively pre-emphasized. A series of samples of the pre-emphasized signal are then obtained and encoded to create a series of digital representations which have a lower order resolution than the samples. The difference between each sample and its corresponding lower resolution digital representation is obtained and combined with the next sample. Decoding of the combined signals takes place in a complementary manner to create an approximate analog output signal, which is then de-emphasized in a manner complementary to the pre-emphasis to produce an analog output signal closely approximating the original analog signal. In a fully digital implementation the samples are converted to a digital format with a higher order resolution; the digital representations are obtained from the digitized samples, and the difference measurements are combined with the samples in their digital format. In a hybrid digital/analog implementation the difference is combined with the analog signal prior to sampling.

Analog phase locked loop

Abstract: A phase locked loop for synchronizing a local digital signal with an incoming data signal is described. Parallel phase and frequency detectors compare the local and incoming signals and generate control pulse signals for controlling the frequency of a voltage controlled oscillator which generates the local digital signal. Logic circuitry is included in both the phase and frequency detectors for adjusting the generated control pulse signals in the event of detection of elongated pulse widths of the incoming data signal, indicating one of either an absence of incoming data signal or a bipolar violation in the event the data signals are ASI encoded. The phase locked loop is characterized by quick pull-in time, large pull-in frequency range, accurate clocking and low cost.

Method and apparatus for determining shaft position and for providing commutation signals

Abstract: The invention provides a method and apparatus for determining the angular displacement of a rotating shaft, and for commutation of a brushless motor. At least two analog sensors, mounted near the shaft, generate phase-displaced analog signals responsive to the angular position of the shaft. A logic circuit produces a digital code indicating the region of the cycle in which the shaft is instantaneously located. An analog multiplexor selects a unique pair of analog signals from the group of the original analog signals and their analog complements, according to the value of the digital code. An analog to digital converter then generates a digital signal proportional to the quotient of the analog signals produced by the multiplexor, and this digital signal, together with the digital code, is used to activate an address in a memory device. The memory device, such as an EPROM, is programmed with a large number of binary digits, which define a train of pulses. As the shaft turns, the addresses in the EPROM are activated in a predetermined order, producing a train of pulses whose frequency is directly proportional to the angular velocity of the shaft. The EPROM can be programmed to generate parallel trains of pulses, including "quadrature" pulses, which encode the direction as well as the displacement of the shaft, and commutation pulses, for controlling a brushless motor. The circuit therefore can be used to monitor the angular displacement of the shaft and, at the same time, to control the motor which drives that shaft.

Delta sigma modulator circuit for an analog-to-digital converter

Abstract: In a delta-sigma modulator for an A/D converter for modulating an analog input signal to produce a modulated signal of a digital form, a first integrator produces a first integral signal indicative of an integral of the difference between the analog input signal and feedback signal, a first delay element delays the first integral signal by one sampling period, a second integrator produces a second integral signal indicative of an integral of the difference between the output of the first delay element and the feedback signal, a first quantizer produces a two-level signal "1" or "0" depending on whether or not the second integral signal is greater than a predetermined reference, and a second quantizer produces a two-level signal "1" or "0" depending on whether or not the first integral signal is greater than a predetermined reference. An output digital signal is produced in accordance with the outputs of the first and the second quantizers. The feedback signal is also produced in accordance with the outputs of the first and the second quantizers.

Apparatus and method for digital compensation of oscillator drift

Abstract: This disclosure concerns digital correction of oscillator drift by providing phase alignment between two clock signals running at nearly the same frequency. Phase alignment is provided by fashioning a delay for one of the clock signals through selection of various lengths of a variable delay path formed from a series of logic circuits. Respective reference signals are derived from the two clocks to be phase-aligned, and the phases of the references are compared in a digital phase comparator. The product of phase comparison controls a digital delay selector to generate a sequence of delay signals corresponding to a sequence of detected phase differences. The delay signal sequence controls the variable digital delay. The variable digital delay outputs a corrected clock signal whose phase is aligned with the phase of the other clock signals. The corrected clock signal is used to produce one reference signal, the other reference signal being derived directly from the other clock signal. A second digital phase comparator compares the phase of the corrected clock signal with a predetermined reference phase of the clock signal from which it is derived. When the phases of the clocks are aligned, the second comparator produces a reset signal which resets the digital selection circuit to a predetermined point in the delay signal sequence, thereby operating the variable digital delay to correct the clock signal to a phase corresponding to the predetermined reference phase.

Binary tree multiprocessor

Abstract: A binary tree multiprocessing array of plural signal processing elements, and having input/output for the array entirely through a root one of the processing elements, includes in each processing element thereof a hardware, pipelined, floating point, multiply/accumulate processing function for cooperating with a procesing element memory and a processing element input/output processing function to perform signal pattern matching of input digital signal sequences provided to and/or through the root processing element with respect to at least one digital signal sequence pattern stored in the memory.

Driver circuit for driving a light emitting element by superimposing an analog sub-information signal over a digital main signal

Abstract: A driver circuit for driving a light emitting element with a signal generated by superimposing an analog sub-information signal over the pulse string of a digital main signal. The driver circuit includes an input interception detector for detecting any interception of the digital main signal, and a gain-controlled amplifier for increasing the gain of the analog sub-information signal when the digital signal is intercepted.

A Parallel Architecture for Discrete Relaxation Algorithm

Abstract: Discrete relaxation techniques have proven useful in solving a wide range of problems in digital signal and digital image processing, artificial intelligence, operations research, and machine vision. Much work has been devoted to finding efficient hardware architectures. This paper shows that a conventional hardware design for a Discrete Relaxation Algorithm (DRA) suffers from O(n2m3) time complexity and O(n2m2) space complexity. By reformulating DRA into a parallel computational tree and using a multiple tree-root pipelining scheme, time complexity is reduced to O(nm), while the space complexity is reduced by a factor of 2. For certain relaxation processing, the space complexity can even be decreased to O(nm). Furthermore, a technique for dynamic configuring an architectural wavefront is used which leads to an O(n) time highly concurrent DRA3 architecture.

Diagnostic system for a digital signal processor

Abstract: A diagnostic system for a digital signal processor, having an input module, an output module and a plurality of successive processing modules defining a signal processing path, monitors various internal test points within each module. Any one of the test points may be connected to a diagnostic bus. The output of the diagnostic bus may be appropriately modified and input to the output module in lieu of the digital signal from the last processing module to provide a diagnostic display.

Fiber optic data transmitting system

Abstract: A fiber optic digital data transmitting system is disclosed which has the capability of transmitting and accurately reproducing digital data signals at the receiver even when the optical signal is attenuated in the fiber optic transmitting medium. A composite signal is produced at the transmitter which is the time coincident sum of the non-zero amplitude of the digital data signal to be transmitted and a time varying signal which encodes each non-zero amplitude of the digital signal and other information. The composite signal modulates an optical carrier signal which is coupled to a fiber optic transmission medium which couples the transmitter to the receiver. At the receiver, the presence of each time varying signal is detected as a non-zero amplitude of the digital signal. Circuitry is are provided in the receiver for producing a pulse in response to the detection of each time varying signal for reproducing the transmitted digital signal and for detecting any information in addition to the non-zero amplitude of the digital signal which has been encoded in the time varying signal. The present invention is compatible with existing PCM systems which utilize threshold detection.

Airflow sensor and control circuit

Abstract: The airflow sensor uses a flow sensing bridge having a thermal element which senses airflow as a function of electrical energy applied to the bridge. Energy is applied to the bridge to maintain the thermal element at a constant temperature and constant resistance. A differential amplifier monitors the balanced and unbalanced state of the bridge and controls the application of energy to the bridge to maintain a balanced state. A microcomputer with analog to digital converter senses the level of energy applied to the bridge and converts this energy level to a digital signal indicative of airflow. The raw digital signal is corrected using calibration lookup tables and thermal compensation correction tables in the microcomputer memory circuits. The microcomputer outputs a variable frequency signal indicative of the measured mass airflow. In the alternative to the differential amplifier, the bridge may be balanced using the microcomputer in a sample and hold voltage to current converter configuration.

Digital Signal Transmission on Power Line Carrier Channels: An Introduction

Abstract: The possibility of transmitting digital signals on power line carrier channels is investigated. An accurate model of the multiconductor transmission line and a rigorous propagation algorithm are used. A computer aided procedure is presented to evaluate channel transient response to any input digital signal code. The discrete convolution method uses the inverse Fourier transform of the channel frequency response in amplitude and phase. The eye diagram approach permits evaluation of channel perfomance. The results obtained in an application on a three-phase long line, confirm the feasibility of the proposed method.

A PSK Group Modem for Satellite Communications

Abstract: A PSK group modem which modulates and demodulates multiple PSK signals en bloc will play an important role in realizing a cost-effective satellite communications system based on the narrowband multicarrier PSK/FDMA technique. This paper briefly discusses its possible applications, and presents a developed PSK group modem including its algorithm, hardware design, and implementation. In the algorithm, filtering of respective PSK signals is effectively carried out by digital signal processing techniques applied to the digital transmultiplexer. Furthermore, in order to compensate for the difference between the operation timing of the PSK group modem and the symbol timing of each input/output data signal, digital signal processings based on a table-look-up method using ROM and a rate-conversion filter with adaptive weighting are proposed for the modulator and demodulator, respectively. An experimental 4-phase PSK group modem has been developed, and experiments have been conducted under various conditions. The measured performance of the developed hardware is also demonstrated.

Apparatus for recording and reproducing digital signals

Abstract: A digital signal recording and reproducing apparatus comprising a dynamic range compression/expansion apparatus. The compression/expansion apparatus (16) receives a digital signal from, for example, an analog-to-digital converter (II) and compresses the dynamic range of the digital signal and the so compressed digital signal is supplied to a recording signal processing circuit (27) in the recording operation mode, while the apparatus receives a digital signal reproduction output from a recording/reproducing head (29, 30) and expands the dynamic range of the reproduced digital signal and the so expanded digital signal is supplied to, for example, a digital-to-analog converter (12) in the reproducing operation mode. The compression/expansion apparatus includes a circuit for controlling the transient response of the apparatus, that is, for controlling the operation of the compression/expansion of the dynamic range of the digital signal during transient of the digital signal so that recording of the digital signal is performed at a high density with a high quality, without suffering breathing effect, overflow, etc.

Video disk with multiplexed video and digital information

Abstract: A recording and reproducing device for frequency division multiplexing of a television video and a digital data signal. The digital signal is interleaved in blocks so that the length of an interleaved block is longer than a video field but shorter than a video frame. The interleaved digital data is recorded so that an end of a group of blocks corresponds to a vertical synchronizing signal for the video signal.

Analog offset compensation technique

Abstract: A method (and system) for correcting an analog signal for undesired signal components comprising the steps of (and means for) receiving the analog signal; digitizing the analog signal to generate a raw digital signal; processing the raw digital signal to generate a digital correction signal; converting the digital correction signal to an analog correction signal; and applying the analog correction signal to the analog signal to generate a corrected analog signal. The method and system may be adapted to correct for a set of undesired components, or to correct a train of analog signals. The method and system may be used for correcting digital signals. In a particular embodiment, the method and system may be used to correct for offset and/or gain nonuniformities in the output signals from detector elements in a focal plane array.