Showing papers on "Digital signal published in 1989"

Digital output transducer

Abstract: Contained within a single housing (120), is a transducer (100) for receiving an acoustic signal, an analog-to-digital converter (108), which changes the output of transducer (100) into a series of digital pulses representing the incoming acoustic signal. The output of the system may be in serial form. This serial output (114) is transmitted (116) to a remote receiver (122) by wires, light, optical fibers, or as radio waves. The receiver's (122) output (124) is applied to a digital system (130), which processes or reconstructs the acoustic signal. The system may include a digital signal processor (300) within the housing (120) for processing the signal (110) prior to transmission. The analog to digital converter may be a delta-sigma oversampling type, or a sub-ranging floating point type, or use adaptive differential pulse code modulation. Power may be derived remotely by transmission over the signal medium.

Bit-serial realizations of a class of nonlinear filters based on positive Boolean functions

Abstract: It is shown that the function of a stack filter can be realized in k-step recursive use of one binary processing circuit. The time-area complexity of the proposed filter is O(k) as compared with O(2/sup k/) for stack filters. The proposed digital realizations are simple and modular in structure, and suitable for VLSI implementation. Analog/digital (A/D) hybrid realizations have the advantage that there is no need for an A/D converter array when the original signals come from an integrated sensor array. An experimental digital rank-order filter with a window size of three and arbitrary number of input bits is designed and implemented in a 3- mu m double-metal polysilicon gate CMOS process. The chip has been fabricated and measurement results are correct with a clock frequency of up to 110 MHz. >

Digital subharmonic sampling down-converter

Abstract: A digital subharmonic sampling converter, for use in an analog IF signal demodulator and the like, includes: an analog-to-digital converter (ADC) means receiving the IF analog signal for conversion to a digital data stream by sampling at a sampling rate frequency substantially equal to 4/(2n+1) times the IF signal frequency, where n is an integer greater than zero. A digital mixer means is used to convert the sampled data to baseband. The interleaved sequential in-phase I data words and quadrature-phase Q data words are then sorted into a pair of concurrent I and Q data word streams.

The role of lossless systems in modern digital signal processing: a tutorial

Abstract: A self-contained discussion of discrete-time lossless systems and their properties and relevance in digital signal processing is presented. The basic concept of losslessness is introduced, and several algebraic properties of lossless systems are studied. An understanding of these properties is crucial in order to exploit the rich usefulness of lossless systems in digital signal processing. Since lossless systems typically have many input and output terminals, a brief review of multiinput multioutput systems is included. The most general form of a rational lossless transfer matrix is presented along with synthesis procedures for the FIR (finite impulse response) case. Some applications of lossless systems in signal processing are presented. >

Electrical power control apparatus and methods

Abstract: Electrosurgery apparatus includes an r.f. power amplifier with an output to a patient electrode. The amplifier is controlled by the voltage of input signals from a control unit which receives a sample of the voltage and current of the output signal. The voltage and current signals are supplied to A/D converters to provide two digital signals that are used to address a look-up table in an EPROM and provide a digital output representative of impedance. A switch is set by the user to the desired mode/power curve and this provides a digital signal which together with the impedance signal is used to address a second look-up table in an EPROM which contains digital representations of the required output voltage of the amplifier to produce the desired power level. An adder compares the required voltage with a feedback of the actual voltage to produce an error signal that is supplied to the amplifier to control its output.

Digital signal processing using waveguide networks

Abstract: Disclosed is a signal processor formed using digital waveguide networks. The digital waveguide networks have signal scattering junctions. A junction connects two waveguide sections together or terminates a waveguide. The junctions are constructed from conventional digital components such as multipliers, adders, and delay elements. The signal processor of the present invention is typically used for digital reverberation and for synthesis of reed, string or other instruments.

Electro-optical analog-to-digital converter and method for digitizing an analog signal

Abstract: An electro-optical analog-to-digital converter having an enhanced effective sample rate. Several embodiments of the electro-optical analog-to-digital converter (10, 100, 150, and 200) are described, each involving either space-division demultiplexing, time-division demultiplexing, or wavelength-division demultiplexing to increase the effective sample rate at which an analog signal provided by a source (36) can be converted to a digital signal using electrical analog-to-digital converters (66). A plurality of light pulses having a constant amplitude are modulated in response to the analog signal and demultiplexed using one of the three different techniques, so that the analog signal is sampled at successive points in time, varying the intensity of light pulses passing through each modulator channel (32, 104). In the space-division demultiplexing approach, light pulses produced by a mode-locked diode laser (12) are split into a plurality of channels and delayed by different time intervals so that the replicated pulses are spaced apart in time prior to being modulated by passage through a modulator array (32). The demultiplexed and modulated light pulses are input to a plurality of photodetectors (56) amplified by a plurality of amplifiers (60 ), and input to a plurality of electrical analog-to-digital converters (64). In the time-division multiplexing approach, either discrete optical switches (108) or an optical switch array (158) is used to transmit successive modulated light pulses into selected photodetectors for conversion to an electrical signal that is input to the analog-to-digital converters. The wavelength-division multiplexing approach uses a plurality of mode-locked diode lasers (210), each having a different characteristic wavelength. Pulses output from the mode-locked diode lasers are generated at different times and provided to a wavelength-division multiplexer (214) where they are combined and input to the modulator. A wavelength-division demultiplexer (220) separates the different wavelength pulses for input to selected photodetectors. For all the embodiments, the effective sample rate corresponds to the number of channels multiplied by the rate at which pulses are produced by the mode-locked laser diodes.

Digital automatic gain control apparatus

Abstract: A digital automatic gain control apparatus is provided which controls gain such that when an analog video signal is converted into digital signals for processing, the input of the A-D converter is maintained at a fixed level, and after the analog signal has been converted into digital form, the output of the digital system circuit is also maintained at a fixed level. In this apparatus, an input signal is passed through an analog variable gain amplifier, the signal is converted into digital form, and the output of an A-D converter is passed through a digital variable gain amplifier. The amplitude level of the output of the digital variable gain amplifier is detected by an amplitude detecting unit and is controlled so as to be equal to a specified reference value. At this time, the analog variable gain amplifier is controlled so that the level of the control signal for controlling the digital variable gain amplifier is equal to a specified reference value, thereby maintaining the signal of the A-D converter at a fixed level. Gain control of the analog signal system and the digital signal system, before and after the A-D converter, is effected by a single amplitude detecting unit.

Small size apparatus for measuring and recording acceleration

Abstract: A small size apparatus for measuring and recording acceleration comprises an acceleration sensor, an A/D converter which converts the output signal of the acceleration sensor to a digital signal, a control element which processes the digital signal, a detachable external memory device which stores data of a change in acceleration and, a battery for supplying electric power to the sensor, the A/D converter, the control element and the external memory device. The small size apparatus is mounted on a moving body to be measured and the entire small size apparatus is driven by the battery. The correct attachment of the external memory device is detected by steps of writing data into a special address, reading the data out thereafter, and comparing the written data and read data. When the read data coincides with the written data, it is judged that the external memory device is correctly attached.

Recording and reproducing apparatus with limited digital copying

Abstract: A composite digital signal received by a recording and reproducing apparatus includes a digital information signal and a control signal. The control signal represents a number of digital copy generation of the associated information signal. The information signal of the received digital composite signal is recorded into recording medium. The information signal is reproduced from the recording medium. During the reproduction of the information signal, a new control signal is generated which represents a number equal to one plus the number represented by the control signal of the received composite digital signal. The new control signal and the reproduced information signal are combined into a new composite digital signal. The new composite digital signal is outputted. A check is made as to whether or not the number represented by the control signal of the received composite digital signal is equal to a predetermined number. When the number represented by the control signal of the received composite digital signal is equal to the predetermined number, the recording of the information signal of the received composite digital signal is inhibited.

Efficient digital beamforming in the frequency domain

Abstract: The formation of steered beams for a linear array of hydrophones is a necessary task in many sonar systems. In this paper, algorithms for beamforming digital signals in the frequency domain are compared for their computational efficiency and suitability for implementation on an array processor. Methods based on the chirp z transform (CZT) and on interpolation using finite‐impulse response (FIR) filters are shown to be the most efficient, although beamforming based on Goertzel’s algorithm is also competitive when the beams are formed in conjugate pairs.

Digital signal processor for providing timbral change in arbitrary audio and dynamically controlled stored digital audio signals

Abstract: A digital audio signal processing technique in which the harmonic content of the output signal varies with the amplitude of an input signal. The preferred embodiment includes an analog to digital converter with sample and hold, a digital signal memory with playback control apparatus, timing circuits, a RAM look-up table to perform non-linear transformation and finally a digital to analog converter. The input signal, which can be an arbitrary audio signal or a digital signal representative of such a signal, is modified by a non-linear transformation means and outputted for reproduction in audible form or stored for subsequent processing.

High speed digital to analog to digital communication system

Abstract: High speed communication of digital information is accomplished using an analog transmission format. A transmitter receiving digital data in parallel multi-bit words converts digital words in conversion clock cycles to a single analog signal relative to a DC level. The transmitter also includes a reference pulse generator which combines a reference pulse with the analog levels generated by the converter to form an analog output for transmission to the receiver. The receiver includes a detector receiving the analog output. In response to the reference pulse, the receiver generates a recovery clock. A flash analog-to-digital converter converts the analog levels in the analog output to multi-bit digital outputs. The parallel multi-bit words are regenerated in recovery clock cycles from sampling the multi-bit digital output once per cycle. Thus, by using a digital to analog to digital system, effective bit rates are achieved that are higher than the switching speeds of the transmitter and receiver.

Detection of overheated railroad wheel and axle components

Abstract: Overheated railroad journal bearings, wheels, and other wheel components on a moving or stationary railroad train are detected by amplifying the current signal from an infrared radiation sensor comprising a pyroelectric cell. A reference temperature is sensed by chopping the incident infrared radiation with an asynchronous shutter that momentarily closes at successive time spacings of shorter duration than the scanning period of the sensor. The amplified signal is converted to a digital signal and processed by a microcontroller and associated hardware and software. The detector automatically and periodically calibrates itself and compensates the temperature signals for any temperature difference between the ambient external temperature and the temperature inside the detector housing. The output signal may be digital or analog.

Method and apparatus for mapping a digital signal carrier to another

Abstract: A DS-3 to 28 VT1.5 SONET Interface Circuit is shown, without using standard intermediate DS-2 and DS-1 Desynchronizer Phase-Lock Loops. The elimination of DS-2 and DS-1 Desynchronizer Phase Lock Loops results in a significant reduction in cost and complexity of SONET interface circuits for the existing asynchronous digital multiplex hierarchy.

Power conservation method and apparatus for a portion of a synchronous information signal

Abstract: A receiver (70) receives a transmitted digital signal having a synchronization signal and information signals The receiver (70) includes a sync acquisition device (76) and sync maintenance device (86) to synchronize to the received synchronization signal and address detect device (80) to detect predetermined signals within the information signals When the address detect device (80) determines that an information signal is substantially different from the predetermined signals, the power conservation device (88) causes power to be conserved for the remainder of the information signal

Computational structures for fast implementation of L-path and L-block digital filters

Abstract: One of the major problems in the multi-DSP (digital signal processor) implementation of L-path and L-block digital filters is the hardware complexity-throughput rate tradeoff The author presents computational structures based on the theory of fast algorithms for short linear convolutions, which are suitable for the implementation of these types of digital filters He also compares the performance of the structures with two previously published ones The comparison shows that the schemes proposed here are faster and that the complexity-throughput tradeoffs can easily be controlled by the designer >

Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions

Abstract: The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

Remote control apparatus for a rotating television camera base

Abstract: A remote control apparatus for a rotating camera base that supports a television camera such that it is rotatable in the horizontal and vertical directions. The remote control apparatus comprises a first controlling circuit that outputs a digital signal for driving and controlling the rotating camera base; a control box including a modulating circuit that outputs a modulated version of the digital signal from the first controlling circuit with a prescribed carrier wave, said control box being electrically connected to the first controlling circuit; a demodulating circuit that recovers the digital signal from the modulated wave from the modulating circuit, said demodulating circuit being provided in the rotating camera base and electrically connected to the modulating circuit; and a second controlling circuit that drives and controls the rotating camera base based on the digital signal from the demodulating circuit, said second controlling circuit being electrically connected to the demodulating circuit.

Digital signal transmission apparatus

Abstract: A digital signal transmission apparatus in which a digital signal having a header block of a predetermined length is transmitted. The header comprises a synchronization signal and auxiliary data. The auxiliary data is made up of first data or second data and a redundant error detection code. The redundant code is formed so that syndrome patterns of the error detection code are different in order to distinguish the block in which the first data is contained as the auxiliary data on the reception side, from the block in which the second data is contained as the auxiliary data so that a plurality of headers having different contents can be distinguished on the reception side.

Direct connect modem deriving power from telephone line

Abstract: A telephone modem which is at least partially powered by electrical power from a telephone line to which it is connected and which is further powered by a local power source, such as power extracted from digital serial data lines to which it is coupled or from a battery source or a combination thereof. Telephone line power is used to operate all analog signal processing, and local power is used to operate the remainder of the modem, including digital signal transmission, reception and manipulation, as well as modem control functions. In a preferred embodiment, optical isolation means provide isolation between differently-powered segments of the modem circuitry. The analog signal processing segment is coupled to the telephone line in a manner which maintains line current requirements and constant a.c. impedance, and regulated power is derived from the intermittent telephone line power source. In a further specific embodiment, charge pump circuitry is employed to extract both positive and negative inverted power from the digital serial data signal line for use as local power.

Integrated telecommunication system with improved digital voice response

Abstract: An integrated telecommunication system for multiple telephone line response and processing having a plurality of interface circuits, each of which is adapted to control the physical connection to a plurality of telephone line channels, control communication on a group of telephone line channels connected thereto. Each interface circuit includes a high speed interface microprocessor and a first data storage associated therewith. A first bus system interconnects the plurality of interface processor circuits to signal processor circuits. Each signal processor module includes a cross-point switch and a high speed digital signal microprocessor for analyzing the incoming signals and compressing the data therein, a second data storage associated therewith, and one or more of a plurality of telecommunication function circuits controlled thereby. A multi-bus system connects each of the plurality of interface processors to each of the plurality of signal processor circuits and to a main system control processor and a third data storage. The high speed processing requirements of each group of telephone lines is performed by the respective interface control processor and a digital signal microprocessor and main system control processor selectively controls the storage of data in the first, second and third data storages and intercommunication functions between the plurality of interface processor circuits and the plurality of signal processor circuits and the function circuits controlled thereby.

Signature analysis apparatus

Abstract: A method and apparatus for developing a digital signal that represents the profile of a movable part such as a bolt. The part is moved by a part carrier between a source of radiant energy and a sensor and the sensor develops a voltage that is a function of the profile of the part. This voltage is processed by a programmed microprocessor. The processing of the voltage and the microprocessor operates to develop a digital representation of the part that does not vary with the changes in speed of the part. The part carrier is moved between the source and sensor and voltage variations due to vertical motion of the part carrier are compensated.

Apparatus and method for testing wooden poles

Abstract: A method of determining the stiffness and condition on a wooden structure. The method consists of initiating the natural vibration of the structure in a band of frequencies that cover at least two of the first five resonant modes of vibration. An electrical response equivalent to the vibration motion of the structure is generated and the electrical response is converted to a digital signal. The resonant frequency of the structure is calculated by analysing the digital signal. By comparing the results with the results obtained using a mathematical model the stiffness and condition of the structure is determined.

Echo measurement arrangement

Abstract: A digital signal processor is provided with the facility to range and converge on each of a plurality of echoes occurring at respective locations along a communications line. Specifically, the digital signal processor is arranged to adaptively process samples of a signal that has been transmitted to the communications line correlated with samples of a signal that have been received from the communications line. In the processing of the samples, the digital signal processor separates and measures the magnitude of each echo that it converges on, beginning with a so-called near-end echo. In addition, the digital signal processor calculates the propagation delay of each echo that it converges on using the number of sampling intervals that have been processed in order to position the processor on the dispersion of that echo.

Local area network modem

Abstract: A local area network modem which meets the stringent signalling requirements of the IEEE 802.4 standard. The modem supports loopback commands by insuring that the receiver and transmitter portions are in phase-synchronism, regardless of the distance between the modem and upper layer control circuitry. An automatic gain control circuit is included which eliminates a number of problems associated with prior designs. The modem's receiver monitors itself to automatically correct drift in phase and automatic gain control adjustment, without intervention from the upper layer. Control (AGC) circuits are particularly susceptible to noise corruption while the receiver is being synchronized. The transmitter uses only two digital signal wires to specify which of a number of functions are to be performed by the transmitter analog components.

Phase unwrapping of digital signals

Abstract: In order to unwrap the phase of a digital signal, the signal's z-plane zeros, which lie close to the unit circle, are located by repeatedly expanding the z-plane in small steps and detecting a zero's crossing of the unit circle. This detection is accomplished by determining the step which gives rise to a maximum change in the phase at any frequency sampling point and across any segment of the unit circle. This method and its associated computer program have been rigorously tested, and the phase was successfully unwrapped in most cases, with the few exceptions involving sequences generated from high-density clusters of zeros. >

Reliability and workability test apparatus for an environmental monitoring system

Abstract: An environmental monitoring system in which a controller is arranged to test the workability and reliability of a plurality of detector units on a cyclic basis. Each unit has an analog sensor and an analog to digital converter for converting the analog sensor voltage to a digital value in a range of 0 to N. Each unit responds to a test instruction to cause the sensor analog output to assume an alarm value. The sensor output is limited to a maximum value that under a no drift condition of the analog to digital converter, its corresponding digital signal value will be intermediate a tolerance range of values, the upper limit of such range being less than N. The controller includes a test routine program for both issuing the test instruction and for determining if the digital signal test value is within the tolerance range and issuing a trouble output indicative of the test value being outside the range. The controller also includes a polling program which directs the polling of the detector units such that a test instruction is sent sequentially to the detector units on successive loop polls, where a loop poll is one poll of all the units coupled to the line.

The architectures and design of a 20-MHz real-time DSP chip set

Abstract: A set of four real-time 20-MHz digital signal processor (DSP) chips has been designed, fabricated, and tested. The chips include a 64-tap programmable FIR (finite impulse response) filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an eight-line 512-pixel video line delay. The circuits were implemented in a 1.5- mu m CMOS process and are fully functional with a 20-MHz clock rate. The processors have reconfigurable windows to allow processing on both one-dimensional and two-dimensional data. The FIR filters can be used in multiprocessor systems to increase the window size and the data precision. >