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Showing papers on "Digital signal published in 1999"


Patent
09 Apr 1999
TL;DR: In this article, a detector detects a first parametric signal responsive to the first input signal passing through a portion of the subject having blood therein and also detects a second parametric response to the second input signal.
Abstract: A method and an apparatus measure blood oxygenation in a subject. A first signal source applies a first input signal during a first time interval. A second signal source applies a second input signal during a second time interval. A detector detects a first parametric signal responsive to the first input signal passing through a portion of the subject having blood therein. The detector also detects a second parametric signal responsive to the second input signal passing through the portion of the subject. The detector generates a detector output signal responsive to the first and second parametric signals. A signal processor receives the detector output signal and demodulates the detector output signal by applying a first demodulation signal to a signal responsive to the detector output signal to generate a first output signal responsive to the first parametric signal. The signal processor applies a second demodulation signal to the signal responsive to the detector output signal to generate a second output signal responsive to the second parametric signal. The first demodulation signal and the second demodulation signal both include at least a first component having a first frequency and a first amplitude and a second component having a second frequency and a second amplitude. The second frequency is a harmonic of the first frequency. The second amplitude is related to the first amplitude to minimize crosstalk from the first parametric signal to the second output signal and to minimize crosstalk from the second parametric signal to the first output signal.

485 citations


Book
01 Jan 1999

398 citations


Journal ArticleDOI
TL;DR: This paper addresses area-speed tradeoffs in the design of the logic block circuits and in the connections between the logic and the routing structure, and proposes a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort.
Abstract: For Pt.I see ibid., vol.7, pp.191-7 (1999). Field-programmable gate arrays (FPGA's) are now widely used for the implementation of digital systems, and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I of this paper, we described the high-level architectural design of a static random-access memory programmable FPGA. This paper will address the circuit-design issues through to the physical layout. We address area-speed tradeoffs in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time intensive. We propose a design style with a minitile that contains a portion of all the components in the logic tile, resulting in less full-custom effort. The minitile is replicated in a 4/spl times/4 array to create a macro tile. The minitile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easy changing of the hard-wired connections in the logic block architecture and the segmentation length distribution in the routing architecture.

253 citations


Patent
04 Feb 1999
TL;DR: In this article, a system for measuring the speed of a person while running or walking along a surface is described, where a single acceleration sensor measures the acceleration in the forward direction and provides an acceleration signal which is amplified and subsequently sampled by an analog to digital converter.
Abstract: A system for measuring the speed of a person while running or walking along a surface. A single acceleration sensor (8) measures the acceleration in the forward direction and provides an acceleration signal which is amplified (10) and subsequently sampled by an analog to digital converter (12). The digital signal is processed by a microprocessor (14) which executes an algorithm that determines the stride length and the stride duration from the digitized acceleration signal and calculates the speed and the distance traversed. The information thus obtained is transmitted by means of a radio frequency transmitter (16) and received by a radio frequency receiver (18) in a watch or other device (2) which comprises a display (20) which can be viewed by the runner or walker. The speed and distance traversed is displaced on the display (20), along with other useful information, such as average speed, maximum speed, total distance traversed, calories expended, and heart beat.

172 citations


Journal ArticleDOI
TL;DR: The exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors.
Abstract: In order to make software applications simpler to write and easier to maintain, a software digital signal-processing library that performs essential signal- and image-processing functions is an important part of every digital signal processor (DSP) developer's toolset In general, such a library provides high-level interface and mechanisms, therefore, developers only need to know how to use algorithms, not the details of how they work Complex signal transformations then become function calls, eg, C-callable functions Considering the two-dimensional (2-D) convolver function as an example of great significance for DSP's, this paper proposes to replace this software function by an emulation on a field-programmable gate array (FPGA) initially configured by software programming Therefore, the exploration of the 2-D convolver's design space will provide guidelines for the development of a library of DSP-oriented hardware configurations intended to significantly speed up the performance of general DSP processors Based on the specific convolver, and considering operators supported in the library as hardware accelerators, a series of tradeoffs for efficiently exploiting the bandwidth between the general-purpose DSP and accelerators are proposed In terms of implementation, this paper explores the performance and architectural tradeoffs involved in the design of an FPGA-based 2-D convolution coprocessor for the TMS320C40 DSP microprocessor available from Texas Instruments Incorporated However, the proposed concept is not limited to a particular processor

168 citations


Patent
Hock C. So1, Sau C. Wong1
22 Jun 1999
TL;DR: In this article, a memory architecture for a nonvolatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines, each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation.
Abstract: A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation. In another embodiment, a shared read circuit generates a read signal that ramps across the range of permitted threshold voltages for the memory cells, and a sense amplifier in each pipeline clocks a sample-and-hold circuit or another temporary storage circuit when the sense amplifier senses a transition in conductivity of a selected memory cell. When clocked, the sample-and-hold circuit or other temporary storage circuit registers a signal that corresponds to the read signal and indicates a data value associated with the voltage of the read signal. In alternative embodiments, the signal registered is the read signal, a converted form of the read signal, or a multi-bit digital signal.

149 citations


Journal ArticleDOI
TL;DR: The proposed digital signal processing technique for measuring the operating frequency of a power system provides correct and noise-free estimates for near-nominal, nominal, and off- Nominal frequencies in about 25 ms, and it requires modest computations.
Abstract: This paper describes the design, computational aspects, and implementation of a digital signal processing technique for measuring the operating frequency of a power system. The technique provides correct and noise-free estimates for near-nominal, nominal, and off-nominal frequencies in about 25 ms, and it requires modest computations. The proposed technique is implemented using a DSP-based board and has been extensively tested using voltage signals obtained from a dynamic frequency source and from a power system. Some test results are presented in the paper.

141 citations


Journal ArticleDOI
TL;DR: In this article, an enhanced weighted least-squares (WLS) design for variable-fractional-delay finite-impulse response (FIFR) filters was proposed.
Abstract: Digital filters capable of changing their frequency response characteristics are often referred to as variable digital filters (VDFs) and have been found useful in a number of digital signal processing applications. An important class of VDFs is the class of digital filters with variable fractional delay. This paper describes an enhanced weighted least-squares design for variable-fractional-delay finite-impulse response filters, which offers improved performance of the filters obtained with considerably reduced computational complexity compared to a recently proposed weighted least-squares (WLS) design method. The design enhancement is achieved by deriving a closed-form formula for evaluating the WLS objective function. The formula facilitates accurate and efficient function evaluations as compared to summing up a large number of discrete terms, which would be time consuming and inevitably introduce additional errors into the design.

138 citations


Patent
Austin H. Lesea1
21 Jun 1999
TL;DR: In this paper, the analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry, and the analog comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage.
Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

124 citations


Journal ArticleDOI
TL;DR: In this article, the propagation of digital and analog signals through media which, in general, are both dissipative and dispersive is modeled using the one-dimensional telegraph equation, and the analysis presented here supports the finding that digital transmission in dispersive media is generally superior to that of analog.
Abstract: In this article, the propagation of digital and analog signals through media which, in general, are both dissipative and dispersive is modeled using the one-dimensional telegraph equation. Input signals are represented using impulsive, Heaviside unit step, Gaussian, rectangular pulse, and both unmodulated and modulated sinusoidal pulse type boundary data. Applications to coaxial transmission lines and freshwater signal propagation, for both digital and analog signals, are included. The analysis presented here supports the finding that digital transmission in dispersive media is generally superior to that of analog. The boundary data (input signals) give rise to solutions of the telegraph equation which contain propagating discontinuities. It is shown that the magnitudes of these discontinuities, as a function of distance, can be found without the need of solving the governing equation. Thus, for digital signals in particular, signal strength at a given distance from the input source can be easily determined. Furthermore, the magnitudes of these discontinuities are found to be independent of both the dispersion coefficient k and the elastic coefficient b. In addition, it is shown that, depending on the algebraic sign of k, one of two distinct forms of dispersion is possible and that for small-time intervals, solutions are approximately independent of k.

115 citations


PatentDOI
TL;DR: In this article, a desired acoustic signal is extracted from a noisy environment by generating a signal representative of the desired signal with processor (30) using a discrete Fourier transform process.
Abstract: A desired acoustic signal is extracted from a noisy environment by generating a signal representative of the desired signal with processor (30). Processor (30) receives aural signals from two sensors (22, 24) each at a different location. The two inputs to processor (30) are converted from analog to digital format and then submitted to a discrete Fourier transform process to generate discrete spectral signal representations. The spectral signals are delayed to provide a number of intermediate signals, each corresponding to a different spatial location relative to the two sensors. Locations of the noise source and the desired source, and the spectral content of the desired signal are determined fron the intermediate signal corresponding to the noise source locations. Inverse transformation of the selected intermediate signal followed by digital to analog conversion provides an output signal representative of the desired signal with output device (90). Techniques to localize multiple acoustic sources are also disclosed. Further, a technique to enhance noise reduction from multiple sources based on two-sensor reception is described.

PatentDOI
TL;DR: In this paper, a method for generating digital audio filters for equalizing a loudspeaker is presented, for a tolerance range for a target response curve of sound level versus frequency for the loudspeaker.
Abstract: A method for generating digital filters for equalizing a loudspeaker. First digital data is provided, for a tolerance range for a target response curve of sound level versus frequency for the loudspeaker. Second digital data is generated, for an actual response curve of sound level versus frequency for the loudspeaker (1010). The first digital data is compared with the second digital data and it is determined whether the actual response curve is within the tolerance range (1020). If the actual response curve is not within the tolerance range, digital audio filters are iteratively generated, and the digital audio filters are applied to the second digital data to generate third digital data for a compensated response curve (1050, 1060, 1070). The frequency, amplitude and bandwidth of the digital audio filters are automatically optimized until the compensated response curve is within the tolerance range or a predetermined limit on the number of digital audio filters has been reached, whichever occurs first (1080).

Patent
Brent Keeth1
24 Nov 1999
TL;DR: In this paper, a bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an external clock signal and is applied to clock a plurality of latches, each latch has input and output terminals and latch successfully latches the delayed digital signal output from the corresponding signal delay circuit.
Abstract: A bus capture circuit captures digital signals applied on respective lines of a bus. The bus capture circuit includes a clock delay circuit that generates an internal clock signal responsive to an external clock signal. The internal clock signal has a fixed delay relative to the external clock signal and is applied to clock a plurality of latches. Each latch has input and output terminals and latches a digital signal applied at the input terminal responsive to the internal clock signal from the clock delay circuit. The bus capture circuit further includes a plurality of signal delay circuits, each signal delay circuit being coupled between a respective bus line and the input terminal of a respective latch. Each signal delay circuit develops a delayed digital signal having a delay time relative to the digital signal applied on the corresponding bus line, and applies the delayed digital signal to the input terminal of the corresponding latch. A control circuit adjusts the delay time of each signal delay circuit as a function of the data eye of the digital signal applied on the input of the signal delay circuit. The corresponding latch successfully latches the delayed digital signal output from the corresponding signal delay circuit. The bus capture circuit may be in a packetized memory device, and may also operate in a monitoring mode during normal operation of the packetized memory device to detect shifts in the data eye of an external command clock signal applied to the packetized memory device and adjust the delay time of all signal delay circuits by a delay adjustment time when such a shift is detected.

Patent
10 Dec 1999
TL;DR: In this paper, a physically compact, wideband signal activity identification, demodulation and characterization, and direction finding device incorporates multiple and cascadable digital signal processing modules operating in asynchronous real time.
Abstract: A physically compact, wideband signal activity identification, demodulation and characterization, and direction finding device incorporates multiple and cascadable digital signal processing modules operating in asynchronous real time. The digital signal processing modules include a device for data buffering, a device for digital signal processing (DSP), and a device for high-speed data routing. The module device for data buffering is composed of, among other memory devices, a First In Tap Out (FITO) data buffer that may be accessed at any point for delay or faster than real time resynchronization by the DSP module device. The module device for digital signal processing function incorporates a general purpose digital processor for respective module calculation of overlapped hyperchannelization Fast Fourier Transforms (FFT). Hyperchannels may be combine in a flexible manner to tailor channel bandwidth for optimum signal spectral detection of signal activity, synthesis filter and tuning, demodulation and recognition, and direction finding. The module device for high-speed data routing is composed of one-to-one, one-to-many, or many-to-one digital data routing functions, and allows flexible ordering of digital signal processing modules.

Patent
25 May 1999
TL;DR: In this paper, a high-speed digital distribution system is presented that includes a transmission line bus that carries modulated digital signals and reference signals, and the bus interface can transmit and receive a reference signal.
Abstract: A high-speed digital distribution system is presented that includes a transmission line bus that carries modulated digital signals and reference signals. The transmission line bus has a first end electrically connected to a bus interface that modulates digital data onto said transmission line bus and demodulates modulated digital data signals that it receives from the transmission line bus. The bus interface can transmit and receive a reference signal. At least one digital component interface is in electromagnetic communication with the transmission line bus, and each digital component interface can also modulate digital data onto the transmission line bus and can demodulate modulated digital data signals received from the transmission line bus, and can transmit and receive a reference signal. The transmission line bus communicates modulated digital data in association with the reference signal between and among an external device connected to the bus interface and the at least one digital component interface. In one embodiment, the digital data is quadrature amplitude modulated with an encoding that uses one to five bits for the phase component and zero to three bits for the amplitude component. In another embodiment the transmission line bus has characteristic impedance and has matched terminations at its first and second ends.

Patent
12 May 1999
TL;DR: In this article, the analog and digital circuits are implemented on a single piece of silicon, and the analog block is turned off during a first data-communication interval while the digital block operates.
Abstract: A communication system uses analog and digital circuits along the same data path in a manner that permits the analog circuitry to avoid adverse affects caused by the digital circuitry. Consistent with one embodiment directed to a signal processing system that detects faint incoming signals, the analog and digital circuits are implemented on a single piece of silicon. In such signal processing systems, noise generated by digital processing blocks can degrade the performance of sensitive analog portions. The effective noise is reduced by causing the analog and digital portions of the system to function during separate time intervals. The noise-generating portions of the system may then be turned off during a first data-communication interval while the analog block operates. The data acquired during this period is stored for subsequent processing by the digital portion during a second shorter data-communication interval. Other aspects are applicable to reception arrangements in which part of the incoming signal may be disregarded without significant degradation in performance of the rest of the system, and other aspects are directed to transmission arrangements in which the inverse of the above reception arrangement is used.

Patent
Ronald D. Smith1
26 Feb 1999
TL;DR: In this article, the requirements of the analog to digital converter may be decreased by decreasing the necessary dynamic range for the analog-to-digital converter by subtracting the first and second signals from each other.
Abstract: In calibrating displays, analog information may be converted into digital information to control the display. The requirements of the analog to digital converter may be decreased by decreasing the necessary dynamic range for the analog to digital converter. This may be done by developing a first calibration signal indicative of a first plurality of pixels of the display and developing a second calibration signal indicative of a second plurality of the display. The first and second signals may be subtracted from each other and that signal may then be converted to a digital signal with reduced dynamic range requirements for the analog to digital converter.

Patent
23 Dec 1999
TL;DR: In this article, a first circuit, a second circuit, and a logic circuit are configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate.
Abstract: An apparatus comprising a first circuit, a second circuit, and a logic circuit. The first circuit may be configured to generate one or more first control signals having a first data rate in response to an input signal having a second data rate and a clock signal having the first data rate. The second circuit may be configured to generate one or more second control signals in response to the input signal and the clock signal. The first logic circuit may be configured to generate the clock signal in response to the one or more first control signals, the one or more second control signals and a third control signal.

Patent
George C. Rosar1
16 Apr 1999
TL;DR: In this article, a body implantable medical apparatus includes circuitry for generating and transmitting a modulated analog data signal, such as a signal containing physiologic sensor data, which can be implemented in a Field Programmable Gate Array (FPGA), in an Application Specific Integrated Circuit (ASIC), or using a digital signal processor.
Abstract: A body implantable medical apparatus includes circuitry for generating and transmitting a modulated analog data signal. A receiver receives and digitally demodulates the modulated analog signal. An analog-to-digital converting circuit produces an amplitude limited modulated digital signal corresponding to the modulated analog signal. The converting circuit includes an amplifier coupled to a receive antenna and a comparator having an input coupled to the amplifier and an output coupled to a digital demodulator. The digital demodulator demodulates the modulated digital signal to produce a digital information signal, such as a signal containing physiologic sensor data. The digital demodulator includes a digital delay line comprising a plurality of shift registers or, alternatively, a plurality of multiple-stage delay blocks each coupled to a tap selection device. The digital delay line includes an input coupled to an output of the converting circuit, an exclusive OR (XOR) gate having a first input coupled to an output of the digital delay line, and a conductor coupled between the input of the digital delay line and a second input of the XOR gate, such that delayed and non-delayed modulated digital signals are respectively applied to the first and second XOR gate inputs to produce a digital information signal at an output of the XOR gate. The digital demodulator may be implemented in a Field-Programmable Gate Array (FPGA), in an Application Specific Integrated Circuit (ASIC) or using a digital signal processor. A control circuit is coupled to the digital demodulator to adjust a rate at which the digital demodulator operates.

Patent
26 Jan 1999
TL;DR: In this paper, the received time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demoded digital signals is received correctly or not.
Abstract: After receiving a time division multiplex signal including a plurality of digital data signals transmitted in accordance with different transmission schemes, the received time division multiplex signal is demodulated by a demodulation circuit, and it is judged by a detection circuit whether each of the demodulated digital data signals is received correctly or not. When it is detected that a digital data signal transmitted by any one of the plurality of different transmission schemes is not received correctly, the relevant digital data signal is replaced by a suitable signal such as a null packet signal which does not affect a correct reception of the remaining digital data signals transmitted by the remaining transmission schemes to form a corrected time division multiplexed signal even if a digital data signal is not received correctly.

Patent
13 May 1999
TL;DR: In this article, a receiver (100) requiring only a single IF SAW filter (120) and an IF amplifier (126) receives signals in both analog format and in digital format, such as the NTSC, PAL and SECAM analog television signal formats and the ATSC and DVB digital television signal format.
Abstract: A receiver (100) requiring only a single IF SAW filter (120) and IF amplifier (126) receives signals in both analog format and in digital format, such as the NTSC, PAL and SECAM analog television signal formats and the ATSC and DVB digital television signal formats. IF signals from the IF amplifier (126) are sub-sampled to digital signal form (130) and are processed by respective analog format (140) and digital format (150) processors. Control circuitry (160) responsive to the presence of certain unique components of the signals in analog format and digital format determine which of the analog format and digital format processors is producing valid data and selects the valid data to be utilized. In a television receiver (100), the unique components of the signals may include carrier signals, synchronization signals, pilot signals and symbol timing, and valid data is applied to a television display.

Journal ArticleDOI
01 Jan 1999
TL;DR: The problem of uncertainty analysis in digital signal processing algorithms is discussed, proposing a method based on a 'white box' approach that has a practical application to some common algorithms for measurements on periodic signals.
Abstract: The problem of uncertainty analysis in digital signal processing algorithms is discussed, proposing a method based on a 'white box' approach. A theoretical uncertainty estimation is carried out first; its results are then confirmed by both simulation and experimental tests. The characteristics of the method are highlighted by means of a practical application to some common algorithms for measurements on periodic signals.

Patent
06 Aug 1999
TL;DR: In this paper, a delta-sigma modulator (196) comprising a first quantizer (202) providing a first digital signal d0(k) representing the input signal g(t), a loop filter (198) with input signal paths (200), a compensating DAC (204), and an array of feedback DACs (162) is designed such that the gain from the input signals g(T) to the loop quantizer(160) is small, ideally zero.
Abstract: A delta-sigma modulator (196) comprising a first quantizer (202) providing a first digital signal d0(k) representing the input signal g(t); a loop filter (198) with input signal paths (200); a loop quantizer (160) providing a corrective digital signal d1(k) representing the loop filter's (198) output signal y(t); an array of feedback DACs (162) D/A converting the sum d(k) = df(k) = d0(k) + d1(k) of the first and the corrective digital signals and injecting feedback signals into the loop filter (198) The loop filter's (198) input note (164) is applied the difference of the input signal g(t) and the global analog feedback signal a3(t) The global feedback signal a3(t) is delayed several clock cycles with respect to the digital output signal d(k) The delay is used to carry out mismatch-shaping and deglitching algorithms in the feedback DACs (162) The feedback DACs' (162) different delays and gain coefficients are designed such that the modulator (196) is stable The filter's input signal paths (200) and the compensating DAC (204) are designed such that the gain from the input signal g(t) to the loop quantizer (160) is small, ideally zero Thus, the loop quantizer's (160) resolving range can be a fraction of the first quantizer's (202) resolving range, whereby the output signal's d(k) resolution can be much higher than the individual resolutions of d0(k) and d1(k) The delta-sigma modulator (196) is well suited for the implementation of high-resolution wide-bandwidth A/D converters Important applications include digital communication systems

Patent
16 Sep 1999
TL;DR: In this article, a multi-clock matched filter for receiving signals with multipath is presented, where the signals may be modulated with a spread-spectrum spreading sequence, or other analog or digital signal.
Abstract: A multi-clock matched filter for receiving signals with multipath. The signals may be modulated with a spread-spectrum spreading sequence, or other analog or digital signal. A number of signal registers (11, 21, 31, 41) store digital samples of the received signal. The gating of digital samples into each of the signal registers is controlled through a plurality of gates (12, 22, 32, 42) by a separate clock timing. The timing sequence may be derived from a common clock (68). A multiplexer (18) sequentially selects each of the signal registers (11, 21, 31, 41), and passes the respective content of each signal register to a matched filter (150). A number of signal path-tracking circuits (17, 27, 37, 47) track each of the multipath signals, and generate the timing sequence for gating signal registers (12, 22, 32, 42).

Patent
Henrique S. Malvar1
26 Feb 1999
TL;DR: In this article, the authors proposed a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT).
Abstract: The present invention is embodied in a system and method for performing spectral analysis of a digital signal having a discrete duration by spectrally decomposing the digital signal at predefined frequencies uniformly distributed over a sampling frequency interval into complex frequency coefficients so that magnitude and phase information at each frequency is immediately available to produce a modulated complex lapped transform (MCLT). The system includes real and imaginary window processors and real and imaginary transform processors. The real and imaginary window processors receive the input signal and apply and compute butterfly coefficients for the real and imaginary parts of the signal to produce resulting real and imaginary vectors, respectively. The real and imaginary transform processors compute spatial transforms on the real and imaginary vectors to produce real and imaginary transform coefficient of the MCLT, respectively. The MCLT is a biorthogonal spectral transformation system, in the sense that the original time domain signal can be reconstructed exactly by an inverse MCLT operator.

Patent
02 Sep 1999
TL;DR: In this article, the analog-side interface circuit 100 A and the digital-side interfaces 100 B are used to detect the logic of the digital signal with a timing that does not include the jitter component that is included in the transmitted digital signal, the detected digital signal logic being used as the basis for generating a new digital signal.
Abstract: An interface circuit that is suitable for use in a recording system and a system for manufacturing optical disks, which is provided with this interface circuit, have an analog-side interface circuit 100 A and a digital-side interface circuit 100 B, these interface circuits being optically linked, either acoustically, or electromagnetically, so as to enable mutual transmitting and receiving of a digital signal therebetween. The interface circuits 100 A and 100 B, which serve as a receiving side with respect to the other sides, detect the logic of the digital signal with a timing that does not include the jitter component that is included in the transmitted digital signal, the detected digital signal logic being used as the basis for generating a new digital signal.

Patent
02 Feb 1999
TL;DR: In this paper, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer, where the demultanexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder.
Abstract: In a digital broadcast receiving apparatus, digital broadcast signals provided by a digital broadcast method are supplied to various types of external units and are effectively utilized. In the above apparatus, a descrambler descrambles a transport stream output from a front end unit and supplies it to a digital interface and a demultiplexer. The demultiplexer extracts from the transport stream a compressed video signal and a compressed audio signal of a program specified by a user, and supplies the extracted signals to an MPEG decoder. The MPEG decoder decompresses the supplied video signal and the audio signal and supplies them to the digital interface, an NTSC encoder, and an audio signal D/A converter. The digital interface supplies either of the transport stream or the decompressed data to a digital external unit under the control of the controller.

Patent
Olli Tapio1
25 May 1999
TL;DR: In this paper, a linearisation and modulation device for a power amplifier is presented, which consists of a digital vector modulator and lineariser for generating a modulated digital signal (IF_MOD) on the basis of digital baseband signals (IIN, QIN) and digital carrier signals (PH_S, PH_C).
Abstract: The present invention discloses a linearisation and modulation device for a power amplifier The linearisation and modulation device comprises a digital vector modulator (103, 104, 105) for generating a modulated digital signal (IF_MOD) on the basis of digital baseband signals (IIN, QIN) and digital carrier signals (PH_S, PH_C); a correction value generating means (114, 108; 114a, 108a) for generating an amplitude correction value (CV_AMAM) and a phase correction value (CV_AMPM) on the basis of said digital baseband signals (IIN, QIN) and on the basis of a non-linearity distortion generated in said power amplifier (6) arranged in a subsequent stage; an amplitude correction means (106) for generating a corrected digital signal (IF_OUT) on the basis of said modulated digital signal (IF_MOD) and said amplitude correction value (CV_AMAM); a phase correction means (111) for generating a corrected phase control signal on the basis of said phase correction value and an output signal of a phase control signal generation means (110); and a carrier signal generating means (112) for generating said carrier signals (PH_S, PH_C) on the basis of an output of said phase correction means (111) With such a device, a combined modulator and lineariser can be constructed, which leads to a compact system

Patent
29 Jun 1999
TL;DR: In this paper, the authors proposed an AGC circuit for an optical PRML read channel that is insensitive to low frequency disturbances of an RF input signal, which includes a VGA amplifier, a low pass filter, an ADC, a baseline Wander Correction Circuit, a digital gain control circuit, and a DAC.
Abstract: AGC Circuitry for an optical PRML read channel that is insensitive to low frequency disturbances of an RF input signal. The AGC Circuitry includes a VGA amplifier, a low pass filter, an ADC, a baseline Wander Correction Circuit, a digital gain control circuit, and a DAC. The VGA amplifier amplifies the RF input signal to produce a second RF signal. The low pass filter filters the second RF signal to produce a first analog signal. The ADC converts the first analog signal into a digital AGC output signal suitable for decoding. The baseline Wander Correction Circuit removes from the digital AGC output signal effects of low frequency disturbance of the RF input signal to produce a second digital signal. The digital gain control circuit controls the gain of the VGA amplifier by producing a digital gain control signal in response to the second digital signal. The DAC for converting the digital gain control signal into the analog gain control signal to be applied to the VGA amplifier, the analog gain control signal being substantially free from effects of low frequency disturbance of the RF input signal.

Patent
29 Dec 1999
TL;DR: In this article, a digital representation of the sine function and of the cosine function of the frequency of each of the signals is derived based on the digital representations of the frequencies.
Abstract: In a system having an input signal set with at least two signals having mutually exclusive frequencies f1 and f2 being part of the input signal set, whose amplitude is represented in an input digital representation, the amplitudes of each of the at least two signals are digitally represented. A digital representation of the frequency of each of the signals is derived. A digital representation of the sine function and of the cosine function of the frequency of each of the signals is derived based on the digital representation of the frequency. The digital representations of each of the sine and cosine functions is mixed with the input digital representation to derive digital representations of the sine and cosine functions of each of the signals. The digital representations of the sine and cosine functions of each of the signals are processed to derive a digital representation of the amplitude of each of the signals.