Showing papers on "Digital signal published in 2001"

Digital Signal Processing with Field Programmable Gate Arrays

Abstract: Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms So the efficient implementation of these algorithms is critical and is the main goal of this book It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems A case study in the first chapter is the basis for more than 40 design examples throughout The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters Each chapter contains exercises The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Quartus II web edition" software This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises

An Implementation of Key-Based Digital Signal Steganography

Abstract: A real-life requirement motivated this case study of secure covert communication. An independently researched process is described in detail with an emphasis on implementation issues regarding digital images. A scheme using stego keys to create pseudo-random sample sequences is developed. Issues relating to using digital signals for steganography are explored. The terms modified remainder and unmodified remainder are defined. Possible attacks are considered in detail from passive wardens and methods of defeating such attacks are suggested. Software implementing the new ideas is introduced, which has been successfully developed, deployed and used for several years without detection.

Integrated digital loop carrier system with virtual tributary mapper circuit

Abstract: An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders an to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the Cus and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.

Real-time digital signal processing

Abstract: Preface. Chapter 1. Introduction to Real-Time Digital Signal Processing. Chapter 2. Introduction to TMS320C55x Digital Signal Processor. Chapter 3. DSP Fundamentals and Implementation Considerations. Chapter 4. Design and Implementation of FIR Filters. Chapter 5. Design and Implementation of IIR Filters. Chapter 6. Frequency Analysis and Fast Fourier Transform. Chapter 7. Adaptive Filtering. Chapter 8. Digital Signal Generators. Chapter 9. Dual-Tone Multi-Frequency Detection. Chapter 10. Adaptive Echo Cancellation. Chapter 11. Speech Coding Techniques. Chapter 12. Speech Enhancement Techniques. Chapter 13. Audio Signal Processing. Chapter 14. Channel Coding Techniques. Chapter 15. Introduction to Digital Image Processing. Appendix A: Some Useful Formulas and Definitions. A.1 Trigonometric Identities. A.2 Geometric Series. A.3 Complex Variables. A.4 Units of Power. References. Appendix B: Software Organization and List of Experiments. Index.

System and method for distributing perceptually encrypted encoded files of music and movies

Abstract: The present invention is a system for transmitting a digital signal which includes an encoder, a perceptual encrypting system and a transmitter. The encoder band-compression encodes a first digital signal as encoded data defining an image. The perceptual encrypting system is coupled to the and perceptually encrypts the encoded data to generate restricted video data as perceptually encrypted encoded data. The transmitter is coupled to the perceptual encrypting system and transmits the perceptually encrypted encoded data. A combined receiver and decoder for the restricted video data as perceptually encrypted encoded data includes a receiver and a decoder. The receiver receives the perceptually encrypted encoded data. The decoder is coupled to the receiver and decodes the perceptually encrypted encoded data to generate low quality video.

Real time correction of a digital pwm amplifier

Abstract: Distortion and noise in high power digital PWM amplifiers is reduced by measuring the difference between the desired output signal and the actual output signal on a pulse by pulse basis. This analog error is converted into a digital signal with an analog to digital converter (ADC). The digital error signal is then used to correct the feedback of the delta sigma modulator in real time. Preferably, more than one moment of the modulator signal is corrected via the feedback. Preferably, the predictable error of the circuitry which is known a priori is also corrected by correcting the delta sigma modulator feedback. A specialized ADC allows the loop delay to be low, without compromising accuracy.

Digital voltage regulator using current control

Abstract: A digitally implemented voltage regulator in which a switching circuit intermittently couples the input terminal and the output terminal in response to a digital control signal. A current sensor generates a digital first feedback signal derived from the current passing through the switching circuit, and a voltage sensor generates a digital second feedback signal derived from the output voltage. A digital controller receives and uses the digital feedback signals to generate the digital control signal.

Speech recognition system

Abstract: A speech recognition system 7 for an automotive vehicle 10 is provided including a microphone receiver 12 for receiving a voice audio signal and converting the same to an analog signal 13, a microphone aimer for giving the microphone receiver 12 a locational bias for reception, an analog to digital converter 15 for converting the analog signal to a digital signal, a speech recognizer 17 for recognizing a voice from the digital signal received from the analog to digital converter 15, an occupant restraint system 22 having an occupant informational system 60/18 to control deployment of the occupant restraint system 22 resultant upon an occupant condition, an occupant restraint system signal generator 18 for signaling the occupant condition to the microphone aimer to locationally bias the reception of the microphone receiver 12.

Control Systems Technology

Abstract: From the Publisher: This book presents All of the major topics in modern analog and digital control systems, along with the practical, applications oriented knowledge and skills needed by technicians. It contains user-friendly conceptual explanations and clearly written mathematical developments. Examples of both Mathcad and MATLAB illustrate computer problem solving—but this book emphasizes the ability to use any suitable software to achieve successful results in solving problems and performing design. Chapter topics include Measurement; Laplace Transforms; Control System Models; Static and Dynamic Response; Stability; Frequency Response Analysis; Root Locus; State Variable Analysis; Introduction to Discrete Control Systems; Z-Transforms and Discrete State-Space Analysis; Digital Signal Representations; Discrete Time Control Systems; Stability of Discrete Control Systems; and Advanced Topics in Control Systems. For engineers and technicians working for companies that integrate control systems with the use of programmable logic controllers.

Portable data device efficiently utilizing its available power and method thereof

Abstract: A portable data device (400) having a power controller (430), a clock generator (428) and a digital circuit (432). The power controller (430) has an output signal. The output signal is representative of available power. The clock generator (428) is coupled to the output signal of the power controller (430) for generating a variable clock rate corresponding to the output signal. The digital circuit (432) is coupled to the clock generator (428), and the digital circuit (432) is controlled by the variable clock rate.

Configuring digital functions in a digital configurable macro architecture

Abstract: A new digital configurable macro architecture is described. The digital configurable macro architecture is well suited for microcontroller or controller designs. In particular, the foundation of the digital configurable macro architecture is a programmable digital circuit block. The programmable digital circuit blocks can be configured to coupled in series or in parallel to handle more complex digital functions. More importantly, the configuration of the programmable digital circuit block is determined by its small number of configuration registers. This provides much flexibility. In particular, the configuration of the programmable digital circuit block is fast and easy since changes in configuration are accomplished by changing the contents of the configuration registers, whereas the contents are generally a small number of configuration data bits. Thus, the programmable digital circuit block is dynamically configurable from one predetermined digital function to another predetermined digital function for real-time processing.

Digital signal receiver for measurement while drilling system having noise cancellation

Abstract: A method is disclosed for reducing noise in a measured telemetry signal The method includes tracking a characteristic of at least one harmonic of a noise component in the measured telemetry signal band The at least one harmonic has a frequency outside a telemetry signal band The characteristic of the noise component is determined for at least one other harmonic thereof The at least one other harmonic has a frequency inside the telemetry signal band A noise reference is generated from the characteristic of the in band harmonic, and the noise reference is combined with the measured telemetry signal to generate a noise-canceled telemetry signal

Fundamentals of Digital Signal Processing

Abstract: 1. Crash Course in Digital Signal Processing. 2. Analog-to-Digital and Digital-to-Analog Conversion. 3. Digital Signals. 4. Difference Equations and Filtering. 5. Convolution and Filtering. 6. z Transforms. 7. Fourier Transforms and Filter Shape. 8. Digital Signal Spectra. 9. Finite Impulse Response Filters. 10. Infinite Impulse Response Filters. 11. DFT and FFT Processing. 12. Hardware for DSPs. 13. Programming DSPs. 14. Signal Processing. 15. Image Processing. 16. Wavelets. References. Appendices. Index.

Digitally-synthesized loop filter circuit particularly useful for a phase locked loop

Abstract: In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In a preferred embodiment, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which requires a small incremental integrated circuit area. The power dissipation of the digital integration block is reduced by incorporating a decimation stage to reduce the required operating frequency of the remainder of the digital integration block.

Real-Time Digital Simulation of Power Electronic Apparatus Interfaced with Digital Controllers

Abstract: This paper presents a new approach for the real-time digital simulation of power electronic controllers in power systems. Digital controllers for power electronic systems present a problem when testing in real-time using a digital simulator due to the discrete nature of their outputs, which are not necessarily in synchronism with the time step of the simulator. The proposed algorithm combines the variable step-size numerical integration method with linear interpolation for the synchronization of a real-time digital simulator and a digital controller. It is shown that lack of such synchronization leads to inaccurate simulation results, specifically with regard to the fundamental and harmonics of the voltage and current signals. Sampling theory is used to model the interaction between a digital simulator and a digital controller. A pulse width modulated (PWM) voltage source converter (VSC) based reactive power compensator system is used as an illustrative example for the simulation.

Method and radio system for digital signal transmission

Abstract: The invention relates to a method and a radio system for transmitting a digital signal. The method comprises the following steps: (300) the transmitter transmits at least a part of the signal via at least two different transmit antenna paths; (302) the transmitter weights the transmit power of the signals to be transmitted via the different transmit antenna paths with respect to one another by means of changeable weighting coefficients determined for each transmit antenna path; (304) the receiver receives the signal. In an embodiment, (306) the transmitter performs measurements on the received signals that were transmitted via the different transmit antenna paths; (308) the receiver signals to the transmitter the weighting coefficient data formed on the basis of the masurements; (312A) the transmitter forms weighting coefficients by means of the weighting coefficient data signalling. In another embodiment, (310) the transmitter forms a quality value for the weighting coefficient data signalling it has received; (312B) the transmitter forms weighting coefficients by means of the quality value of the weighting coefficient data signalling and the signalling itself.

Car reverse alerting and multi-functional display

Abstract: A car reverse alerting and multi-functional display is disclosed. A display and trumpet are mounted on the multi-functional rear view mirror of a car. A charge coupling device, a microphone, and a car reverse sensor for monitoring the images, sounds and distance at a backside of the car are installed. The monitored analog electronic signals are decoded through a decoder so that the electronic signal is converted into a digital signal from an analog signal. Then, these signals are transferred to the multi-functional rear view mirror by cable or wireless devices. Then the signals are processed by a central processing unit. Then an image signal is outputted to a display for displaying; and meanwhile, the display outputs the sound signal from the microphone. The driver can reverse a car safely from the image and speech alert.

Method and apparatus for multi-sensor processing

Abstract: Multi-sensor system for real-time embedded monitoring of object senses mixed-mode object conditions. Various sensors separately provide disparate analog signals representing different measurable attributes regarding sensed object. For example, such sensors may separately sense temperature, pressure, or other biometric value. Then, according to specified rule set or other qualifying parameters, a digital signal is generated by a processor or controller to indicate one or more condition of the sensed object according to certain sensor input values. Additionally, such multi-sensor scheme may be coupled to a digital network or otherwise coupled thereto for simulation and/or communication applications.

Spread spectrum signaling for speech watermarking

Abstract: The technique of embedding a digital signal into an audio recording or image using techniques that render the signal imperceptible has received significant attention. Embedding an imperceptible, cryptographically secure signal, or watermark, is seen as a potential mechanism that may be used to prove ownership or detect tampering. While there has been a considerable amount of attention devoted to the techniques of spread-spectrum signaling for use in image and audio watermarking applications, there has only been a limited study for embedding data signals in speech. Speech is an uncharacteristically narrow band signal given the perceptual capabilities of the human hearing system. However, using speech analysis techniques, one may design an effective data signal that can be used to hide an arbitrary message in a speech signal. Also included are experiments demonstrating the subliminal channel capacity of the speech data embedding technique developed here.

Priority handling of voice over data in a voice-over-internet protocol processor

Abstract: An apparatus for processing packets in a multimedia terminal has a media access controller to send and receive packets from a network. A digital signal processor converts a series of incoming real-time transfer protocol packets into an incoming digital signal and converts an outgoing digital signal into a series of outgoing real-time transfer protocol packets. A compression-decompression unit decompresses the incoming digital signal and generates an output signal to an output device and compresses an input signal from an input device and generates an outgoing digital signal. A central processing unit sends and receives transmission control protocol packets. The apparatus can store a packet in one of a plurality of queues in a buffer and assign a priority to the packet based on whether the packet is a real-time transfer protocol packet or a transfer control protocol packet.

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Abstract: In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.

Signal transmission apparatus and method for optical base station

Abstract: A signal transmitting apparatus for an optical base station is disclosed. According to the invention, a base station outputs a digital IQ signal to an optical connecting unit. The optical connecting unit processes the digital IQ signal digitally, and transmits the digital signal over an optical network to a remotely located optical base station. The remote station digitally processes the signal before converting to an RF signal for transmission. The invention advantageously decreases signal loss and noise associated with analog processing in the optical connecting units and remote stations in the related art. System reliability is also improved.

MEMS-based electrically isolated analog-to-digital converter

Abstract: An isolated-ADC and a method for providing isolated analog-to-digital conversion are disclosed The isolated-ADC includes a microelectromechanical system (MEMS), a comparator, and a digital-to-analog converter (DAC) The MEMS includes a beam element supported from a substrate for movement with respect to an axis, first and second actuators and a sensor The first and second actuators are capable of exerting respective forces upon the beam element causing the beam element to move in response to analog input and feedback signals, respectively The sensor detects changes in position of the beam element and produces a position signal indicative thereof The comparator generates a digital signal based upon a comparison of the position signal with a reference value Based on the digital signal, the DAC generates the feedback signal, and the isolated-ADC produces a digital output signal

Apparatus and method for detecting DVI connectors of a digital video display device

Abstract: An apparatus and a method for determining a type of DVI (Digital Visual Interface) connector connected to a digital video display device, wherein the apparatus utilizes a first resistor connected between a voltage source and a node; a second resistor connected between the node and a ground terminal; a DVI receptacle connected to the DVI connector, the DVI receptacle having a plurality of digital signal sockets connected to receive digital signals output from a host and a plurality of analog signal sockets connected to receive analog signals output from the host, the node being connected to a predetermined one of the analog signal sockets; and a controller connected to the node, the controller determining the DVI connector to be a DVI-D (digital only) type connector when a low voltage is detected at the node, and determining the DVI connector to be a DVI-I (digital and analog) type connector when a high voltage is detected at the node.

PLL circuit, data detection circuit and disk apparatus

Abstract: A PLL circuit is disclosed which extracts phase difference information of a high S/N ratio from a readout signal uses the phase difference information for PLL control. An A/D converter samples the input signal to produce a digital signal. A pattern string detector identifies a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputs pattern string identification information which indicates an identification result. A phase difference generator outputs phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter. A loop filter, a D/A converter and a voltage controlled oscillator generate a clock signal from the phase difference information to control the sampling timing of the A/D converter.

Apparatus and method for seamlessly upgrading the firmware of an intelligent electronic device

Abstract: An intelligent electronic device (IED) includes a power monitoring circuit operative to monitor a parameter of a portion of a power distribution system and generate an analog signal representative thereof. An analog to digital converter couples with the power monitoring circuit and operates to convert the analog signal to a digital signal representative thereof. A processor couples with the analog to digital converter and operates to implement power management functionality and generate power management data. The IED also includes a first non-volatile memory operative to store first program code for execution by the processor. The processor operates to access a second non-volatile memory in the external function module via the interface. The second non-volatile memory includes a second program code and operates to replace the first program code in the first non-volatile memory with the second program code.

CMOS digital optical navigation chip

Abstract: A CMOS digital integrated circuit (IC) chip on which an image is captured, digitized, and then processed on-chip in substantially the digital domain. A preferred embodiment comprises imaging circuitry including a photo cell array for capturing an image and generating a representative analog signal, conversion circuitry including an n-bit successive approximation register (SAR) analog-to-digital converter for converting the analog signal to a corresponding digital signal, filter circuitry including a spatial filter for edge and contrast enhancement of the corresponding image, compression circuitry for reducing the digital signal storage needs, correlation circuitry for processing the digital signal to generate result surface on which a minima resides representing a best fit image displacement between the captured image and previous images, interpolation circuitry for mapping the result surface into x- and y-coordinates, and an interface with a device using the chip, such as a hand-held scanner. The filter circuitry, the compression circuitry, the correlation circuitry and the interpolation circuitry are all advantageously embodied in an on-chip digital signal processor (DSP). The DSP embodiment allows precise algorithmic processing of the digitized signal with almost infinite hold time, depending on storage capability. The corresponding mathematical computations are thus no longer subject to the vagaries of CMOS chip structure processing analog signals. As a result, precise and accurate navigation enables a predictable, reliable and manufacturable design. Parameters may also be programmed into the DSP's “software,” making the chip tunable, as well as flexible and adaptable for different applications.

Residue-compensating A/D converter

Abstract: An analog-to-digital converter system [50D] processing an input signal g, which can be either a discrete-time or a continuous-time signal. A first quantizer [154] generates a first digital signal d0(k), representing the sum of the input signal, g, and a dithering signal, y0. A digital-to-analog converter [156] generates an analog feedback signal, α, representing accurately the first digital signal, d0(k). The DAC [156] may be linearized by the use of mismatch-shaping techniques. A filter [158] generates the dithering signal, y0, by selectively amplifying in the signal band the residue signal, r0, defined as the difference of the input signal, g and the analog feedback signal α. Optional signal paths [166][168] are used to minimize the closed-loop signal transfer function from g to y0, which ideally will be zero. An analog compensation signal, m0, which is described by a well-controlled relationship to the residue signal, r0, is extracted from the filter [158]. Ideally, the closed-loop signal transfer function from g to m0 will be zero, or at least small in the signal band. A second quantizer [160] converts the analog compensation signal, m0, into a second digital signal, dm0(k). The two digital signals, d0(k) and dm0(k), are filtered individually and then added to form the overall output signal, dg(k). The second digital filter [164] has a low signal-band gain, which implies that the sensitivity to signal-band errors caused by the second quantizer [160] will be low. The output signal, dg(k), is a highly-accurate high-resolution representation of the input signal, g. Circuit imperfections, such as mismatch, gain errors, and nonlinearities, will cause only noise-like errors having a very low spectral power density in the signal band. The invention facilitates the implementation of uncalibrated highly-linear high-resolution wide-bandwidth A/D converters [50D], e.g., for use in digital communication systems, such as xDSL modems and other demanding consumer-market products for which low cost is of the essence.