Showing papers on "Digital signal published in 2003"

Integrated protection, monitoring, and control system

Abstract: A method and system for monitoring and controlling a power distribution system is provided. The system includes a plurality of circuit breakers and a plurality of node electronic units. Each node electronic unit is mounted remotely from an associated circuit breaker that is electrically coupled with one of the node electronic units. The system also includes a first digital network, and a first central control unit. The first central control unit and the plurality of node electronic units are communicatively coupled to the first digital network. The method includes receiving digital signals from each node electronic unit at the central control unit, determining an operational state of the power distribution system from the digital signal, and transmitting digital signals to the plurality of node electronic units such that the circuit breakers are operable from the first central control unit.

Method and apparatus for sensing a vehicle crash

Abstract: A sensor system for initiating deployment of an occupant protection apparatus in a motor vehicle, such as an airbag, to protect an occupant of the vehicle in a crash. The system includes a sensor mounted to the vehicle for sensing accelerations of the vehicle and producing an analog signal representative thereof; an electronic converter for receiving the analog signal from the sensor and for converting the analog signal into a digital signal, and a processor which receives the digital signal. The processor includes a pattern recognition system and produces a deployment signal when the pattern recognition system determines that the digital signal contains a pattern characteristic of a vehicle crash requiring occupant protection. A deployment initiation mechanism is coupled to the processor and, responsive to the deployment signal, initiates deployment of the occupant protection apparatus.

An all-digital analog-to-digital converter with 12-/spl mu/V/LSB using moving-average filtering

Abstract: A compact, high-resolution analog-to-digital converter (ADC) especially for sensors is presented. The basic structure is a completely digital circuit including a ring-delay-line with delay units (DUs), along with a frequency counter, latch, and encoder. The operating principles are: (1) the delay time of the DU is modulated by the analog-to-digital (A/D) conversion voltage and (2) the delay pulse passes through a number of DUs within a sampling (= integration) time and the number of DUs through which the delay pulse passes is output as conversion data. Compact size and high resolution were realized with an ADC having a circuit area of 0.45 mm/sup 2/ (0.8-/spl mu/m CMOS) and a resolution of 12 /spl mu/V (10 kS/s). Its nonlinearity is /spl plusmn/0.1% FS per 200-mV span (1.8-2.0 V), for 14-b resolution. Sample holds are unnecessary and a low-pass filter function removes high-frequency noise simultaneously with A/D conversion. Thus, the combination of this ADC and a digital filter that follows can eliminate an analog prefilter to prevent the aliasing before A/D conversion. Also, both this ADC can be shrunk and operated at low voltages, so it is an ideal means to lower the cost and power consumption. Drift errors can be easily compensated for by digital processing.

Isolation system with digital communication across a capacitive barrier

Abstract: An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

Point-to-multipoint digital radio frequency transport

Abstract: A digital radio frequency transport system that performs bi-directional simultaneous digital radio frequency distribution is provided. The transport system includes a digital host unit and at least two digital remote units coupled to the digital host unit. The bi-directional simultaneous digital radio frequency distribution is performed between the digital host unit and the at least two digital remote units.

Method and system for monitoring power supplies

Abstract: An electrical power (AC/DC) monitoring system remotely monitoring batteries and electrical power systems through a call center, providing continual monitoring, monthly reports, near real time viewing and service response. Modular by design, a plurality of individual input modules, which receive an analog voltage input, convert this signal to a digital format and send the digital signal to a central control which collects the data, then, at scheduled intervals, sends the collected data to a web server which contains the main software for the system. This software performs data comparisons, charts trends, predicts failures, plans and schedules service visits, then archives the data for future references. Alarm notifications are provided to the customer via Email, office phone (land line), cell phone (wireless), PDA, pager, etc. and can also be sent to a service provider to initiate the service response.

Cellular signal enhancer

Abstract: A low-cost user portable signal enhancer unit for extending service coverage of wireless communications to a user in a desired area of limited coverage. The enhancement supports an increase of signal power levels to allow wireless communication usage in a location, such as a small office or home office environment where the original cellular signals are weak or unreliable. A base station signal is enhanced by a bi-directional amplifier device (BDA), which receives a base station signal, amplifies the signal power and retransmits the amplified signal in a first signal path to a user in close proximity. The bi-directional amplifier also receives a user signal, amplifies the signal power and retransmits the amplified signal to the base station in a second separate signal path. Dual polarized antennas can receive and transmit the respective signals at opposite polarizations to increase isolation of the signals.

Apparatus and method for digital image correction in a receiver

Abstract: An apparatus and method for performing digital image correction in a receiver. In one embodiment, a receiver circuit may include an IQ signal source configured to provide a digital signal comprising in-phase (I) and quadrature (Q) components, such as an IQ mixer in combination with an analog to digital converter, for example. The receiver circuit may also include an image correction unit coupled to the IQ signal source and configured to combine the digital signal with a complex image correction factor. The image correction unit may be implemented using a digital signal processor under the control of associated program instructions, for example. In one specific implementation of the receiver circuit, the image correction unit may be configured to combine the digital signal with the complex image correction factor using a cross-accumulation operation.

Method and apparatus for real-time transport of multi-media information in a network

Abstract: In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same

Abstract: A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digital signal is stored in an associated storage circuit and defines a timing offset between the corresponding digital signal and the clock. The clock is output along with each digital signal having the timing offset defined by the corresponding phase command and the digital signals are captured responsive to the clock and evaluated to determine if each digital signal was successfully captured. A phase adjustment command adjusts the value of each phase command. These operations are repeated for a plurality of phase adjustment commands until respective final phase commands allowing all digital signals to be successfully captured is determined and stored in the storage circuits.

Continuous-time digital signal processing

Abstract: Digitally processing quantised (but not sampled) signals produces no aliasing and reduces the in-band quantisation error. Techniques for accomplishing such processing are proposed. Experimental evidence is included.

Power amplifier linearization

Abstract: A system for linearizing the output of a high power amplifier (HPA) designed to transmit an RF modulated signal includes in its transmit section a digital up-converter for processing baseband input signals and generating a desired digital RF waveform, T(s). The desired digital RF waveform T(s) is then fed to a digital predistorter circuit for producing a predistorted digital RF waveform P(s)T(s) which, as modified, may be applied via a high sampling speed high linearity digital to analog converter to the high power amplifier (HPA) to produce an output signal which is a linear function of the baseband input signal. The digital predistorter circuit may be of the adaptive type or of the predictive type. Circuits embodying the invention may include encoding circuitry for converting multi-bit signals to a serial stream of single-bit pulses for enabling simplification in the digital to analog conversion. In accordance with the invention, corrections for non-linearity of the HPA may be made directly on the RF waveform using ultra-high speed superconducting electronics (SCE) and decreasing the time delay between sensing a transmitted signal and generating a correcting (linearizing) signal.

Distributed digital antenna system

Abstract: An optical medium, such as fiber, is tapped to provide an antenna port (135, 136, 137, 138) wherever radio service coverage is desired. Each antenna port (135, 136, 137, 138) is a bi-directional remote unit (105, 106, 107, 108) that receives a digital optical signal from a host unit (101) and transforms the signal to a radio frequency signal for transmission by the remote unit (105, 106, 107, 108). The remote unit (105, 106, 107, 108) receives radio frequency signals that are converted to digital signals and summed with signals from other remote units and converted to an optical signal for transmission to the host unit.

Digital system bus for use in low power instruments such as hearing aids and listening devices

Abstract: A low-voltage, low-power, synchronous, bidirectional, time-multiplexed, serial communication, scalable system bus carrying a number of signals over a fewer number of wires between a master device and peripheral devices or between peripheral devices. One of the wires carries a composite digital signal that includes a data signal and a synchronizing signal, though other combinations are contemplated. The system bus can support more peripheral devices than there are available time slots, and supports interrupt polling and servicing. In addition, peripheral devices that include an electro-mechanical or electro-acoustical component connected to the system bus can also communicate directly to each other without using the system bus. The system bus can be implemented in low voltage, low power devices, including listening devices such as hearing instruments and headsets, portable telephones, and personal digital assistants.

Digital speckle correlation for strain measurement by image analysis

Abstract: This paper is concerned with small strain measurement utilizing the numerical processing of digital images. The proposed method has its theoretical basis in digital signal analysis and, from a methodological point of view, it can be considered as an extension to digital images of the wellknown white light speckle photography technique. That conventional method is based on the analysis of photographic plates that are exposed twice (before and after the specimen deformation) with the image of a random speckle pattern that has been previously printed on the test piece surface. The digital speckle correlation advantages consist of requiring a very simple specimen preparation and, mainly, of allowing the strain field computation just by numerical elaboration of the acquired images. In this paper, the theoretical basis of the technique and some valuable improvements to the known analogous methodologies are presented. Finally, test results for an application of digital speckle correlation are shown and advantages and disadvantages of the technique are elaborated. In addition, further developments in this area are discussed.

Method for combining transfer functions with predetermined key creation

Abstract: A method for combining transfer functions with predetermined key creation. In one embodiment, digital information, including a digital sample and format information, is protected by identifying and encoding a portion of the format information. Encoded digital information, including the digital sample and the encoded format information, is generated to protect the original digital information. In another embodiment, a digital signal, including digital samples in a file format having an inherent granularity, is protected by creating a predetermined key. The predetermined key is comprised of a transfer function-based mask set to manipulate data at the inherent granularity of the file format of the underlying digitized samples.

Ultra-wideband high data-rate communication apparatus and associated methods

Abstract: An RF transmitter includes a reference signal generator, a signal generator, and a mixer. The reference signal generator provides a reference signal that has a prescribed or desired frequency. The signal generator provides an operating signal in response to a selection signal. The operating signal has a frequency that equals the frequency of the reference signal multiplied by a number. The mixer mixes the operating signal with another signal to generate a transmission signal. An RF receiver includes a first mixer, a second mixer, an integrator/sampler, and a signal generator. The first mixer receives as its inputs an input RF signal and a second input signal, and mixes its input signals to generate a mixed signal. The integrator/sampler receives the mixed signal and processes it to provide an output signal. The signal generator provides an operating signal in response to a selection signal. The operating signal has a frequency equal to the frequency of a reference signal, multiplied by a number. The second mixer mixes the operating signal with a template signal to generate the second input signal of the first mixer.

Digital signal encoding method, decoding method, encoding device, decoding device, digital signal encoding program, and decoding program

Abstract: The sampling frequency of a digital signal is converted from 96 kHz to 48 kHz for each frame by a down-sampling unit (13). The signal converted is compressed/encoded and output as a main code Im. A local signal corresponding to the main code Im is converted to a signal of sampling frequency of, for example, the original 96 kHz by an up-sampling unit (16) and an error signal between the this signal and an input digital signal is generated. Bits of a sample string of error signals are rearranged by rearrangement/encoding unit (18) and output as an error code Pe. At a decoding side, by using the main code Im and the error code Pe, it is possible to obtain a highly faithful reproduction signal or a reproduction signal based only on the main code Im.

Ultra-wideband high data-rate communications

Abstract: System and methods for generating ultra-wide band communication signal including: filtering a digital data pulse having a data clocking rate by mixing a filter-function pulse with the digital data pulse; generating a harmonic of a clock oscillator which appears as a center frequency of emission of frequency spread spectrum signal; and mixing the filtered digital data pulse with the harmonic of the clock oscillator signal, characterized in that the clock oscillator frequency, the data clocking rate, and the center frequency of signal emissions are harmonically related are disclosed.

Applications of convex optimization in signal processing and digital communication

Abstract: In the last two decades, the mathematical programming community has witnessed some spectacular advances in interior point methods and robust optimization. These advances have recently started to significantly impact various fields of applied sciences and engineering where computational efficiency is essential. This paper focuses on two such fields: digital signal processing and communication. In the past, the widely used optimization methods in both fields had been the gradient descent or least squares methods, both of which are known to suffer from the usual headaches of stepsize selection, algorithm initialization and local minima. With the recent advances in conic and robust optimization, the opportunity is ripe to use the newly developed interior point optimization techniques and highly efficient software tools to help advance the fields of signal processing and digital communication. This paper surveys recent successes of applying interior point and robust optimization to solve some core problems in these two fields. The successful applications considered in this paper include adaptive filtering, robust beamforming, design and analysis of multi-user communication system, channel equalization, decoding and detection. Throughout, our emphasis is on how to exploit the hidden convexity, convex reformulation of semi-infinite constraints, analysis of convergence, complexity and performance, as well as efficient practical implementation.

Efficient interpolator for high speed timing recovery

Abstract: A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Modulation of a digital input signal using a digital signal modulator and signal splitting

Abstract: A digital signal modulator modulates a digital input signal (507) to drive a load (324) such as an opposed current amplifier or other opposed current converter. In one embodiment, a digital signal modulator modulates a digital input signal. Even and odd samples (S3) of the input signal propagates along two respective channels (signal paths PWMn, PWMp), which include further digital processing capabilities, such as pulse width modulation, to generate output signals appropriate for the topology of a load. Additionally, a bias signal (Vb) may be modulated with the digital input signal. By utilizing digital signal processing to modulate the input signal, various processing technologies are applied to the input signal.

A single-chip tuner for DVB-T

Abstract: A new architecture is presented for a single-chip tuner for digital terrestrial television, based on existing double conversion and direct conversion topologies. The new design forms part of a mixed-signal Digital Video Broadcasting-Terrestrial (DVB-T) receiver system, employing digital signal processing at baseband to ensure minimal performance requirements for the analog circuitry. To evaluate the potential performance of this new tuner/receiver system, high-level system simulations have been performed, followed by the construction of a prototype DVB-T receiver using a custom-designed analog ASIC which integrates all analog tuner blocks (including channel filtering) on one chip. Measured results from this chip, implemented in a 20-GHz bipolar technology, show an overall third-order input referred intercept point of 116 dB/spl mu/V, a noise figure of 14 dB and an automatic gain control range of 71.4 dB, drawing 250 mA at a 5-V supply.

Radio transmission frequency digital signal generation

Abstract: The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.

Low skew clock input buffer and method

Abstract: An input buffer includes first and second cross-coupled differential amplifiers. Each amplifier drives a buffer signal from a first logic state to a second logic state at a first slew rate when an input signal transitions from a first logic state to a second logic state and a complementary input signal transitions from the second logic state to the first logic state, and drives the buffer signal from the second logic state to the first logic state at a second slew rate when the input signal transitions are the complement of these previous transitions. An output circuit generates a first edge of an output signal when the buffer signal from the first amplifier transitions from the first logic state to the second logic state and generates a second edge of the output signal when the buffer signal from the second amplifier transitions from the first to the second logic state.

Wave shaping for an implantable medical device

Abstract: In the embodiment of the invention, apparatus and method provide flexibility in generating a stimulation waveform (1901, 1903, 2101) (that comprises at least a stimulation pulse) to an electrode (2611, 2613, 2627, 2629) of an ImplantableNeuro Stimulator (INS). The waveform (1901, 1903) is synthesized for each rate period interval (1902). A portion of the rate period interval is identified, in which the portion comprises at least one phase (2109, 2111, 2113). During each phase, the stimulation waveform is synthesized by a waveform controller (1001) and a waveform generator (1003, 1005). The waveform controller utilizes waveform parameters, e.g. the initial value, final value, and step time duration (2405), to form a digital signal to the waveform generator. The waveform generator utilizes the digital signal to form the synthesized waveform (2101).

An automated floating-point to fixed-point conversion methodology

Abstract: We propose a floating-point to fixed-point conversion (FFC) methodology for digital VLSI signal processing systems. The past techniques used to facilitate FFC are first reviewed, followed by a description based on a statistical approach and global optimization which allows a high degree of automation.

High speed analog to digital converter

Abstract: An analog to digital converter includes a reference ladder, a track-and-hold amplifier tracking an input signal with its output signal during the phase φ 1 and holding a sampled value during, a coarse analog to digital converter having a plurality of coarse amplifiers each inputting a corresponding tap from the reference ladder and the output signal, a fine analog-to-digital converter having a plurality of fine amplifiers inputting corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers, a clock having phases φ 1 and φ 2 , a circuit responsive to the clock that receives the output signal, the circuit substantially passing the output signal and the corresponding taps to the fine amplifiers during the phase φ 2 and substantially rejecting the output signal and the corresponding taps during the phase φ 1 , and an encoder converting outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

Clocked cascading current-mode regulator with high noise immunity and arbitrary phase count

Abstract: A clocked cascadable power regulator including synchronization logic and PWM control logic. The synchronization logic receives a clock signal and asserts a digital output signal synchronized with the clock signal in response to assertion of a digital input signal. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The regulator may be used alone or cascaded with other similar regulators for implementing a multiphase power converter with multiple channels. The clocked cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. In the cascaded configuration, there is one clock common to all channels which ensures that the phase separation between the channels is symmetrical to within the jitter tolerance of the common clock.

High capacity reversible watermarking for audio

Abstract: A digital watermark can be seen as an information channel, which is hidden in a cover signal. It is usually designed to be imperceptible to human observers. Although imperceptibility is often achieved, the inherent modification of the cover signal may be viewed as a potential disadvantage. In this paper, we present a reversible watermarking technique for digital audio signals. In our context reversibility refers to the ability to restore the original input signal in the watermark detector. In summary, the approach works as follows. In the encoder, the dynamic range of the input signal is limited (i.e. it is compressed), and part of the unused bits is deployed for encoding the watermark bits. Another part of these bits is used to convey information for the bit-exact reconstruction of the cover signal. It is the purpose of the watermark detector to extract the watermark and reconstruct the input signal by restoring the original dynamic range. In this study we extensively tested this new algorithm with a variety of settings using audio items with different characteristics. These experiments showed that for 16bit PCM audio, capacities close to 1-bit per sample can be achieved, while perceptual degradation of the watermarked signal remained acceptable.