Showing papers on "Digital signal published in 2011"

Scaling Up Digital Circuit Computation with DNA Strand Displacement Cascades

Abstract: To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.

Decodable indicia reading terminal with combined illumination

Abstract: A decodable indicia reading terminal can comprise a laser-based scanner, an imager-based scanner, a central processing unit (CPU), and an illumination assembly. The laser-based scanner can include a laser source, a photo-detector, and an analog-to-digital (A/D) converter. The laser source can be configured to emit a laser beam onto a substrate bearing decodable indicia. The photo-detector can be configured to receive a beam of a variable intensity reflected by the decodable indicia, and to output a first analog signal representative of the variable intensity. The A/D converter can be configured to convert the first analog signal into a first digital signal. The imager-based scanner can include a multiple pixel image sensor, an imaging lens, and an A/D converter. The imaging lens can be configured to focus an image of the decodable indicia on the image sensor. The A/D converter can be configured to convert into a second digital signal a second analog signal read out of the image sensor and representative of light incident on the image sensor. The CPU can be configured to output a decoded message data corresponding to the decodable indicia by processing the first digital signal and/or the second digital signal. The illumination assembly can include an indicator light bar and an illumination light bar. The ON/OFF state and color of the indicator light bar can reflect the state of the decodable indicia reading terminal. The illumination light bar can be configured to generate a high intensity illumination for illuminating the substrate bearing the decodable indicia. The wavelength of the light generated by the indicator light bar can be substantially equal to the wavelength of the light generated by the illumination light bar, and the light generated by the illumination light bar can have a very low perceived intensity.

Signal loss detector for high-speed serial interface of a programmable logic device

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

High data rate transmitter and receiver

Abstract: A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

Liquid crystal display device and electronic device

Abstract: To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A high-performance digital system for electrical capacitance tomography

Abstract: This paper describes a recently developed digital-based data acquisition system for electrical capacitance tomography (ECT). The system consists of high-capacity field-programmable gate arrays (FPGA) and fast data conversion circuits together with a specific signal processing method. In this system, digital phase-sensitive demodulation is implemented. A specific data acquisition scheme is employed to deal with residual charges in each measurement, resulting in a high signal-to-noise ratio (SNR) at high excitation frequency. A high-speed USB interface is employed between the FPGA and a host PC. Software in Visual C++ has been developed to accomplish operational functions. Various tests were performed to evaluate the system, e.g. frame rate, SNR, noise level, linearity, and static and dynamic imaging. The SNR is 60.3 dB at 1542 frames s−1 for a 12-electrode sensor. The mean absolute error between the measured capacitance and the linear fit value is 1.6 fF. The standard deviation of the measurements is in the order of 0.1 fF. The dynamic imaging test demonstrates the advantages of high temporal resolution of the system. The experimental results indicate that the digital signal processing devices can be used to construct a high-performance ECT system.

Personal communication device with hearing support and method for providing the same

Abstract: The present invention is related to a personal communication device arranged for providing hearing support. The personal communication device comprises an input for receiving an audio signal, programmable processing means and an output for outputting the processed signal. The programmable processing means is arranged for performing a filtering operation on a digital version of the audio signal in a first signal path based on parameter settings and for providing control logic for determining the parameter settings based on information on user preferences, on audiological information and on information on the listening situation, in which the personal communication device is used, obtained via sound environment analysis of the received audio signal and/or via sensing means of the personal communication device, so that the programmable processing means is operable as a hearing loss compensation module arranged for outputting a hearing loss compensated signal. The programmable processing means further has a second signal path in parallel with the first signal path, said second signal path comprising a module for transfer function calculation arranged for receiving the digital version of the audio signal and the parameter settings and for determining the filter coefficients of the filtering means based on the parameter settings and the digital version of the audio signal.

Microcontrolled electrocardiographic monitoring circuit with feedback control

Abstract: A microcontrolled electrocardiographic monitoring circuit (10) with feedback control is provided. An input signal path (23) includes an electrode (12a), a low pass filter (13a), and an amplifier (13b) connected in-line. The electrode (12a) senses an input signal and the amplifier (13b) outputs a filtered amplified output signal. A microcontroller circuit (11) includes an input codec, analog-to-digital converter (14), and feedback generation module. The analog-to-digital converter (14) converts the filtered amplified output signal into a data stream (31) of discrete digital values. The feedback module identifies a pairing of drive resistor settings matched to each discrete digital value, which are output as a digital feedback signal. The output signal path (24) includes an electrode (12b) and a buffer (20) connected in-line. A pair of drive resistors (21a, 21b) is connected in parallel to an input terminal of the buffer (20) and to the output terminals of the feedback module. Each drive resistor is adjusted according to the digital feedback signal, and the electrode (12b) provides an output signal.

Signal transmission device, electronic device, and signal transmission method

Abstract: A signal transmission device includes: at least one of a first communication device that transmits a control signal as a wireless signal and a second communication device that receives the wireless signal transmitted from the first communication device to reproduce the control signal, wherein the wireless signal for the control signal is transmitted separately from a wireless signal for a transmission subject signal which is transmitted between a third communication device and a fourth communication device.

Solid-state imaging device

Abstract: Disclosed is a solid-state imaging device capable of calculating the difference in charge obtained by photoelectric conversion, and capable of a high level of integration A solid-state imaging device (30) is provided with an AD converter (36) which is provided with: a first comparator (60) which outputs a signal corresponding to a first analogue signal of a first pixel (10a or 10b) by comparing said first analogue signal with a reference voltage supplied from the reference voltage generation unit (52) which generates a reference voltage which gradually changes; a second comparator (62) which outputs a signal corresponding to a second analogue signal of a second pixel (10c or 10d) by comparing said second analogue signal with the reference voltage supplied by the reference voltage generation unit (52); a difference circuit (64) which finds the difference between the signal corresponding to said first analogue signal and the signal corresponding to said second analogue signal and outputs a difference signal; and a counter circuit (68) which counts the number of pulses in a pulse sequence corresponding to the aforementioned difference signal and converts said difference signal into a digital signal

Amplifier and amplifying method

Abstract: An amplifier that modulates a carrier frequency according to a digital signal and amplifies the modulated signal includes a determining portion that determines at least one of a sound quality required for the digital signal, a sound source of the digital signal, and a type of sound of the digital signal, a carrier frequency setting portion that sets a carrier frequency according to a result of the determination, and a pulse-width modulating portion that pulse-width modulates the carrier frequency according to the digital signal.

Methods of transmitting information to mobile devices using cost effective card readers

Abstract: A method of transmitting information to a mobile device includes providing a card reader is provided with a read head, a slot for swiping a magnetic stripe of a card and device electronics that includes an analog front-end and a microcontroller. The analog to digital front end is coupled to a processing element in the microcontroller. A raw magnetic head signal is received at the analog to digital front end. The raw magnetic head signal is converted into a processed digital signal that the microcontroller can interpret. An output jack output jack signal is delivered to the mobile device.

Method and apparatus for real time multiplexing with receiver and antenna array elements

Abstract: A method of signal processing, or corresponding apparatus, includes providing multiple analog receive signals at respective antennas and selecting one antenna at a time in an iterative manner, to cycle through the antennas and provide a multiplexed analog signal. The multiplexed analog signal is filtered at a filter to pass a predetermined frequency band. The multiplexed analog signal is sampled at a single analog to digital converter to generate a multiplexed digital signal. The multiplexed digital signal is demultiplexed to generate multiple digital signals for digital processing. Sharing a receiver and ADC among multiple antennas results in reduced cost and power. Such cost and power reductions in turn enable larger antenna arrays than are available with prior art techniques, thereby promoting increased throughput and coverage.

Signal processing device, signal processing method, and signal processing program

Abstract: Provided is a signal processing device for effectively detecting a sudden change in an input signal. This signal processing device is equipped with a conversion means for converting the input signal to an amplitude-component signal and a phase-component signal in the frequency band. In addition, the signal processing device is equipped with a calculation means for calculating the characteristics of the amplitude component signal and the phase-component signal obtained from the conversion means. The signal processing device is further equipped with a determination means for determining whether there is a possibility of a sudden change in the input signal, on the basis of the characteristics calculated by the calculation means.

Brain–Muscle–Computer Interface: Mobile-Phone Prototype Development and Testing

Abstract: We report prototype development and testing of a new mobile-phone-based brain-muscle-computer interface for severely paralyzed persons, based on previous results from our group showing that humans may actively create specified power levels in two separate frequency bands of a single surface electromyography (sEMG) signal. EMG activity on the surface of a single face muscle site (auricularis superior) is recorded with a standard electrode. This analog electrical signal is imported into an Android-based mobile phone and digitized via an internal A/D converter. The digital signal is split, and then simultaneously filtered with two band-pass filters to extract total power within two separate frequency bands. The user-modulated power in each frequency band serves as two separate control channels for machine control. After signal processing, the Android phone sends commands to external devices via a Bluetooth interface. Users are trained to use the device via visually based operant conditioning, with simple cursor-to-target activities on the phone screen. The mobile-phone prototype interface is formally evaluated on a single advanced Spinal Muscle Atrophy subject, who has successfully used the interface in his home in evaluation trials and for remote control of a television. Development of this new device will not only guide future interface design for community use, but will also serve as an information technology bridge for in situ data collection to quantify human sEMG manipulation abilities for a relevant population.

Systems and methods for flyback power converters with switching frequency and peak current adjustments based on changes in feedback signals

Abstract: System and method for regulating a power converter. The system includes a first comparator configured to receive a first input signal and a second input signal and generate a first comparison signal based on at least information associated with the first input signal and the second input signal, a pulse-width-modulation generator configured to receive at least the first comparison signal and generate a modulation signal based on at least information associated with the first comparison signal, a driver component configured to receive the modulation signal and output a drive signal to a switch to adjust a primary current flowing through a primary winding of the power converter, and a voltage-change-rate detection component configured to sample the feedback signal to generate a first sampled signal for a first modulation period and to sample the feedback signal to generate a second sampled signal for a second modulation period.

Digital-to-Analog Converter

Abstract: A system and method for converting a digital signal to an analog signal is provided The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements

Method of transmitting information from efficient communication protocol card readers to mobile devices

Abstract: A method is provided of transmitting information with a communication protocol to a mobile device. A card reader is provided with a read head that has a slot for swiping a magnetic stripe of a card, an output jack and device electronics that includes a microcontroller. The read head is used to read data on a magnetic stripe of a card. A raw magnetic signal is produced indicative of data stored on the magnetic stripe. The raw magnetic head signal is converted into a processed digital signal that the microcontroller can interpret. A synchronous Manchester encoded stream is produced that makes a greater number of 0 crossings. A Manchester encoded stream output jack signal is delivered to the mobile device through the output jack.

Wireless signal transceiver and blind spot detection system

Abstract: A wireless signal transceiver for a blind spot detection system includes a first substrate, a radio-frequency processing unit formed on the first substrate for transmitting a wireless signal and receiving a reflecting signal of the transmitted wireless signal, and a complex programmable logic device controlled by a digital signal processor for controlling operations of the radio-frequency processing unit according to at least a control command of the digital signal processor, so as to detect whether an object exists within a specific range.

Cost effective card reader configured to be coupled to a mobile device

Abstract: A has a read head configured to be coupled to a mobile device. The read head has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. Device electronics are provided with an analog front-end and a microcontroller. The analog to digital front end is coupled to a processing element in the microcontroller. The analog to digital front end receives a raw magnetic head signal and converts it into a processed digital signal that the microcontroller can interpret. The microcontroller produces a signal. An output jack is adapted to be inserted in a port of the mobile device and deliver an output jack signal to the mobile device.

Experimental demonstration and optimisation of a synchronous clock recovery technique for real-time end-to-end optical OFDM transmission at 11.25Gb/s over 25km SSMF

Abstract: A simple, digital signal processing-free, low-cost and robust synchronous clocking technique is proposed and experimentally demonstrated, for the first time, in a 64-QAM-encoded, 11.25Gb/s over 25km SSMF, real-time end-to-end optical OFDM (OOFDM) system using directly modulated DFB laser-based intensity-modulation and direct-detection (IMDD). Detailed experimental investigations show that, in comparison with the common clock approach utilised in previous experimental demonstrations, the proposed clocking technique can be implemented to achieve no system BER performance degradation or optical power budget penalty and more importantly to improve system stability. As a viable synchronous clocking solution for real-time OOFDM transmission, this work is a vital step towards the realisation of practical OOFDM transmission systems and has particular significance for synchronisation of OOFDM multiple access-based passive optical networks where highly accurate synchronisation of all network elements is essential.

Solid-state imaging apparatus

Abstract: A solid-state imaging apparatus comprising a plurality of pixels generating a photoelectric conversion signal, a column amplifying unit corresponding to columns of the pixels, for outputting a first and second signals generated by amplifying the photoelectric conversion signal at a smaller first gain and larger second gain respectively, an analog to digital converter ( 21 ) for converting the first and second signals from an analog signal to a digital signal, a comparing unit ( 224 ) for inputting the digital signal from the analog to digital converter, level-shifting into the same gain level the first and second signals converted by the analog to digital converter, and thereafter detecting a gain error between the level-shifted first and second signals, and a correction unit ( 226 ) for correcting the first and second signals based on the gain error.

Card reader with efficient encryption

Abstract: A card reader has a housing, read head and device electronics that receive a raw signal from the read head and converts it into a processed digital signal that the microcontroller can interpret. A microcontroller with associated logic resources and code receives a digital signal from the device electronics and creates an encrypted and signed message based on the contents of the signal. An output jack is provided.

System and Method for Controlling a Switched-Mode Power Supply

Abstract: In an embodiment, a method of operating a switched-mode power supply includes producing an error signal based on a difference between a power supply output voltage and a reference voltage. A clock frequency is produced that is proportional to the error signal up to maximum frequency, and a sensed current signal is produced that is proportional to a current in switched-mode power supply. The error signal is summed with the sensed current signal to produce a first signal, and the first signal is compared to a first threshold. The method also includes producing a first edge of a drive signal at a first edge of the clock signal, and producing a second edge of the drive signal when the first signal crosses the first threshold in a first direction based on the comparing, where the second edge opposite the first edge.

Methods of transmitting information from efficient encryption card readers to mobile devices

Abstract: A method of transmitting encrypted information to a mobile device and a payment service uses a card reader. The card reader has device electronics that include a microcontroller with logic resources with code and an output jack. A raw magnetic head signal is received from a reading of the card in the slot. The raw magnetic head signal is converted into a processed digital signal that the microcontroller can interpret. The logic resources and the code create both an encryption and signed signal. An encrypted and signed output jack message is delivered to the mobile device through the output jack based on the contents of the signal, with at least a portion of the output jack signal being encrypted.

Card reader with communication protocol

Abstract: A card reader has a read head positioned in the housing. The read head is configured to be coupled to a mobile device. The read head has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. Device electronics are provided that include a microcontroller. The device electronics receives a raw magnetic head signal and converts it into a processed digital signal that the microcontroller can interpret. The microcontroller produces a synchronous Manchester encoded stream that makes a greater number of 0 crossings. An output jack is adapted to be inserted in a port of the mobile device and deliver a Manchester encoded stream output jack signal to the mobile device.

Low-to-medium power single chip digital controlled dc-dc regulator for point-of-load applications

Abstract: A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.

Method And Apparatus For Signal Compression And Decompression

Abstract: In one embodiment, the method of compressing a digital signal includes reducing redundancies in the digital signal, scaling a block of samples output from the reducing step by a scaling factor, and quantizing the scaled samples to produce compressed samples The digital signal being compressed may be a digital radio frequency signal

Circuit and method for optimizing dynamic range in a digital to analog signal path

Abstract: A circuit for maximizing dynamic range in a digital to analog signal path comprises an input for receiving an input signal, a first gain stage coupled to the input having a first gain setting, an second gain stage coupled to the first gain stage, the second gain stage having an second gain setting, a controller configured to selectively increase the first gain setting and decrease the second gain setting according to the input signal level and an output coupled to the second gain stage for transmitting an output signal. A method for maximizing dynamic range in a digital to analog signal path comprises detecting a digital input signal level, detecting a desired user gain level, applying a first gain to the digital input signal, converting the digital input signal into an analog signal, and applying a second gain to the analog signal, wherein the first and second gain are selectively and inversely manipulated according to the digital input signal while maintaining a desired user gain level.

Digital amplitude modulation

Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.