Showing papers on "Digital signal published in 2016"

Digital Signal Processing A Computer Based Approach

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Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time

Abstract: We present a unit that performs continuous-time hybrid approximate computation, in which both analog and digital signals are functions of continuous time. Our 65 nm CMOS prototype system is capable of solving nonlinear differential equations up to 4th order, and is scalable to higher orders. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC + SRAM + DAC). Digitally assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chip makes possible arbitrary nonlinearities and achieves 16× lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 $\mu$ s to several hundred $\mu$ s, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern microcontroller for the same RMS error.

Triboelectric Nanogenerator as a Self-Powered Communication Unit for Processing and Transmitting Information.

Abstract: In this paper, we demonstrate an application of a triboelectric nanogenerator (TENG) as a self-powered communication unit. An elaborately designed TENG is used to translate a series of environmental triggering signals into binary digital signals and drives an electronic-optical device to transmit binary digital data in real-time without an external power supply. The elaborately designed TENG is built in a membrane structure that can effectively drive the electronic-optical device in a bandwidth from 1.30 to 1.65 kHz. Two typical communication modes (amplitude-shift keying and frequency-shift keying) are realized through the resonant response of TENG to different frequencies, and two digital signals, i.e., "1001" and "0110", are successfully transmitted and received through this system, respectively. Hence, in this study, a simple but efficient method for directly transmitting ambient vibration to the receiver as a digital signal is established using an elaborately designed TENG and an optical communication technique. This type of the communication system, as well as the implementation method presented, exhibits great potential for applications in the smart city, smart home, password authentication, and so on.

Fingerprint detection device and mobile terminal

Abstract: Disclosed are a fingerprint detection device and a mobile terminal. The fingerprint detection apparatus comprises a capacitive fingerprint sensor and a capacitive touch control chip which is electrically connected to the capacitive fingerprint sensor; wherein the capacitive fingerprint sensor is configured to collect fingerprint information and convert the fingerprint information to an analog signal; and the capacitive touch control chip is configured to convert the analog signal to a digital signal, and generate fingerprint image information according to the digital signal. As compared with the dedicated control chip in the related art, the capacitive touch control chip has mature design and manufacture technique, and thus the manufacture and application costs are lower.

Generator for digitally generating electrical signal waveforms for electrosurgical and ultrasonic surgical instruments

Abstract: Disclosed is a method of generating electrical signal waveforms by a generator. The generator includes a digital processing circuit, a memory circuit in communication with the digital processing circuit, the memory circuit defining a lookup table, a digital synthesis circuit in communication with the digital processing circuit and the memory circuit, and a digital-to-analog converter (DAC) circuit. The method includes storing, by the digital processing circuit, phase points of a digital electrical signal waveform in the lookup table defined by the memory circuit, wherein the digital electrical signal waveform is represented by a predetermined number of phase points, wherein the predetermined number phase points define a predetermined wave shape. Receiving a clock signal by the digital synthesis circuit. Retrieving, by the digital processing circuit, a phase point from the lookup table. Converting, by the digital processing circuit, the retrieved phase point to an analog signal.

Aliasing Reduction in Clipped Signals

Abstract: An aliasing reduction method for hard-clipped sampled signals is proposed. Clipping in the digital domain causes a large amount of harmonic distortion, which is not bandlimited, so spectral components generated above the Nyquist limit are reflected to the baseband and mixed with the signal. A model for an ideal bandlimited ramp function is derived, which leads to a postprocessing method to reduce aliasing. A number of samples in the neighborhood of a clipping point in the waveform are modified to simulate the Gibbs phenomenon. This novel method requires estimation of the fractional delay of the clipping point between samples and the first derivative of the original signal at that point. Two polynomial approximations of the bandlimited ramp function are suggested for practical implementation. Validation tests using sinusoidal, triangular, and harmonic signals show that the proposed method achieves high accuracy in aliasing reduction. The proposed 2-point and 4-point polynomial correction methods can improve the signal-to-noise ratio by 12 and 20 dB in average, respectively, and are more computationally efficient and cause less latency than oversampling, which is the standard approach to aliasing reduction. An additional advantage of the polynomial correction methods over oversampling is that they do not introduce overshoot beyond the clipping level in the waveform. The proposed techniques are useful in audio and other fields of signal processing where digital signal values must be clipped but aliasing cannot be tolerated.

Digital quaternion logarithm signal processing system and method for images and other data types

Abstract: A system and method for improving the detail of an input digital signal, such as a signal comprising a two dimensional image, can be implemented by computing first and second order gradients of the input signal. These gradients can be represented as quaternions. The logarithm of the quaternions can be used to determine the magnitude and orientation of gradient vectors in the input signal. This gradient magnitude and gradient orientation information can be used to construct an output digital signal that has greater detail than the input digital signal.

Adaptive Digital Signal Predistortion for Nonlinear Communication Systems Using Successive Methods

Abstract: Highly-efficient operation of communication systems requires effective compensation of nonlinear distortion with memory. The main contributor to nonlinearity is the high-power amplifier (HPA) when operated close to saturation. This results in two major detrimental effects: spectral regrowth causing interference in adjacent frequency bands and in-band distortion in the form of constellation warping and clustering. This paper introduces a novel family of adaptive digital signal predistortion schemes that successively modifies the HPA input to drive nonlinear distortion with memory toward zero. This family of schemes is capable of suppressing the spectral regrowth and in-band distortion simultaneously, while keeping the HPA operating efficiently close to saturation. In addition, the proposed solution offers the system designer a beneficial tunability feature to select the levels of suppression. Reduced-complexity Volterra model is adopted and is implemented on-the-fly to cope with systems with high degree of nonlinearity and large memory span. Furthermore, the proposed schemes are made adaptive by applying stochastic gradient method offline during training phase to effectively deal with nonlinear systems whose characteristics are unknown a priori. Extensive computer simulations demonstrate that the proposed adaptive family of predistortion schemes approaches the performance of the perfectly predistorted solution, and can considerably outperform techniques based on adaptive inverse, commonly adopted in the literature.

Interference cancellation apparatus and method

Abstract: Embodiments of the present invention provide an interference cancellation apparatus and method. The method includes: receiving a radio frequency receive signal by using a main receive antenna; canceling a first-type self-interference component in the radio frequency receive signal according to a radio frequency reference signal, to generate a first processed signal; acquiring the reconstructed self-interference signal according to a self-interference channel parameter and the radio frequency reference signal; canceling a second-type self-interference component in the first processed signal according to the reconstructed self-interference signal to generate a second processed signal; performing down-conversion processing on the second processed signal to generate a third processed signal; performing analog to digital conversion on the third processed signal to generate a digital signal; and acquiring a digital baseband reference signal, and performing self-interference channel estimation according to the digital baseband reference signal and the digital signal to acquire the self-interference channel parameter.

Comparison of digital signal-signal beat interference compensation techniques in direct-detection subcarrier modulation systems.

Abstract: Single-polarization direct-detection transceivers may offer advantages compared to digital coherent technology for some metro, back-haul, access and inter-data center applications since they offer low-cost and complexity solutions. However, a direct-detection receiver introduces nonlinearity upon photo detection, since it is a square-law device, which results in signal distortion due to signal-signal beat interference (SSBI). Consequently, it is desirable to develop effective and low-cost SSBI compensation techniques to improve the performance of such transceivers. In this paper, we compare the performance of a number of recently proposed digital signal processing-based SSBI compensation schemes, including the use of single- and two-stage linearization filters, an iterative linearization filter and a SSBI estimation and cancellation technique. Their performance is assessed experimentally using a 7 × 25 Gb/s wavelength division multiplexed (WDM) single-sideband 16-QAM Nyquist-subcarrier modulation system operating at a net information spectral density of 2.3 (b/s)/Hz.

Unfolding-synthesis technique for digital pulse processing. Part 1: Unfolding

Abstract: The unfolding-synthesis technique is used in the development of digital pulse processing systems used in radiation measurements. This technique is applied to digital signals obtained by digitization of analog signals that represent the combined response of the radiation detectors and the associated signal conditioning electronics. The salient features of the unfolding-synthesis technique are first the unfolding of the digital signals into unit impulses, followed by the synthesis of digital signal processing systems with unit impulse responses equivalent to the desired pulse shapes. Part 1 of this paper covers the unfolding part of this technique.

Phase-mode based superconducting logic

Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.

Multi-path analog front end and analog-to-digital converter for a signal processing system with low-pass filter between paths

Abstract: In accordance with embodiments of the present disclosure, a processing system comprising may include a plurality of processing paths and a filter. The plurality of processing paths may include a first processing path and a second processing path, wherein the first processing path is configured to generate a first digital signal based on an analog input signal and the second processing path is configured to generate a second digital signal based on the analog input signal. The filter may have a corner frequency and may be configured to generate a filtered digital output signal combining spectral components of the first digital signal lower than the corner frequency and spectral components of the second digital signal higher than the corner frequency to generate a filtered digital signal.

Novel DSP Receiver Architecture for Multi-Channel Visible Light Communications in Automotive Applications

Abstract: This paper presents a novel visible light communication receiver architecture, designed for automotive applications. A crucial problematic in this area is the design of a suitable receiver able to face the problems caused by the dynamic situations, by the long distances and also by the environmental conditions. In such circumstances, a solution would be to adapt the communication’s data rate to channel conditions, meaning that the communication would take place using different data rates, depending on the signal-to-noise ratio (SNR) and the message priority. Considering the digital filtering a better performance, the proposed architecture considers the usage of digital signal processing as an alternative to the analog signal treatment. The visible light communication receiver proposed in this paper addresses the above-mentioned issues and enables a robust communication even at low SNR.

In-pixel differential transconductance amplifier for adc and image sensor architecture

Abstract: An image sensor comprises a first die with an array of pixels and a second die. The first die and second die are stacked together. A first in-pixel part of an analog-to-digital converter (ADC) outputs at least one current signal. The first in-pixel part of the ADC is a Differential Transconductance Amplifier includes a first differential input for receiving the analog signal and a second differential input for receiving a reference signal. There is at least one output bus connected between the first in-pixel part of the ADC on the first die and the second part of the ADC on the second die. The first part of the ADC is adapted to output the at least one current signal to the at least one output bus, and the second part of the ADC is adapted to receive the at least one current signal and to generate a digital signal.

Modular and scalable digital multimedia mixer

Abstract: A modular multimedia platform includes a chassis into which a variety of modular input/output units, referred to as ports, may be inserted. The units may acquire an input signal and convert it to high precision digital information, or convert a digital signal to an analog signal and output the analog signal (or digital output may be provided). Multiple chassis can be connected together to increase the number of ports. A tag unit may be attached to any device coupled to a port. Each tag has a unique identification number to uniquely identify the device to which it is attached.

American Clinical Neurophysiology Society Guideline 4: Recording Clinical EEG on Digital Media.

Abstract: Digital EEG recording systems are now widely available and relatively inexpensive. They offer multiple advantages over previous analog/paper systems, such as higher fidelity recording, signal postprocessing, automated detection, and efficient data storage. This document provides guidance for the creation of digital EEG recordings including (1) documentation of patient information, (2) notation of information during the recording, (3) digital signal acquisition parameters during the recording, (4) storage of digital information, and (5) display of digital EEG signals.

Method of calibrating a high power amplifier for a radio frequency power measurement system

Abstract: A method for calibrating a set of devices, each device comprising an amplifying component and a measuring component that outputs a digital signal indicative of radio frequency power detected at the amplifying component, includes selecting a frequency from a set of frequencies; selecting a phase value from a set of phase values; selecting a power level from a set of power levels; setting a subset of the set of devices to output signal of the selected frequency, the selected phase value and the selected power level; measuring a forward power level and a backward power level; processing the measurements of the forward and backward power levels to calibrate the digital signal output from the measuring component of each of the set of devices; and encoding the calibrated digital signal output into non-volatile memory.

Digital Active Gate Drives using sequential optimization

Abstract: This paper presents a digital Active Gate Drive (AGD) methodology for power semiconductor devices. The inherent latency limitation of digital signal processing systems is addressed by a sequential optimization procedure that uses voltage and current signals recorded at the previous switching edge to develop an optimized gate drive waveform for the next switching edge. Experimental results using a half-bridge circuit operating at 180 V/100 A show that the proposed scheme is capable of minimizing switching losses whilst constraining the overvoltage peaks occurring at turn-on and turn-off to as low as 200 V and 300 V respectively.

Design and Analysis of Enhanced Modulation Response in Integrated Coupled Cavities DBR Lasers Using Photon-Photon Resonance

Abstract: In the last few decades, various solutions have been proposed to increase the modulation bandwidth and, consequently, the transmission bit-rate of semiconductor lasers. In this manuscript, we discuss a design procedure for a recently proposed laser cavity realized with the monolithic integration of two distributed Bragg reflector (DBR) lasers allowing one to extend the modulation bandwidth. Such an extension is obtained introducing in the dynamic response a photon-photon resonance (PPR) at a frequency higher than the modulation bandwidth of the corresponding single-section laser. Design guidelines will be proposed, and dynamic small and large signal simulations results, calculated using a finite difference traveling wave (FDTW) numerical simulator, will be discussed to confirm the design results. The effectiveness of the design procedure is verified in a structure with PPR frequency at 35 GHz allowing one to obtain an open eye diagram for a non-return-to-zero (NRZ) digital signal up to 80 GHz . Furthermore, the investigation of the rich dynamics of this structure shows that with proper bias conditions, it is possible to obtain also a tunable self-pulsating signal in a frequency range related to the PPR design.

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI

Abstract: As CMOS devices continue to scale down in voltage and area, digital-based high-speed serial I/Os [1] become increasingly competitive with analog-based designs [2,3]. In addition to offering the PVT-independent performance of digital functions and superior power and area scaling to future technology nodes, digital-based I/Os can support advanced line modulation techniques that will become necessary as long-reach electrical channel data rates scale to 56Gb/s and beyond. The key enablers of a digital receiver are power and area efficient analog to digital conversion (ADC) and digital channel equalization. This paper describes the design of a 25Gb/s 2-level digital serial line receiver including a ¼-rate 5b flash ADC, an 8-tap feed-forward equalizer (FFE), an 8-tap decision-feedback equalizer (DFE), and a baud-rate clock and data recovery circuit (CDR). The receiver features a flash ADC, which employs a new power and area efficient slicer design capable of achieving high-precision (∼1mV) threshold accuracy with an associated on-chip calibration system. The 32nm SOI CMOS receiver achieves error-free operation with margin on a reflective transmission-line channel with 40dB half-baud loss.

Analog and digital dimming control for led driver

Abstract: A control circuit includes an input terminal for receiving an input signal, which maybe either a digital input signal or an analog input signal, and the control circuit is configured to provide a digital control signal in response to the input signal. The control circuit may include a mode detection circuit for determining whether the input signal is a digital signal or an analog signal and providing a mode signal, a multiplexer circuit configured to select either a digital reference signal or an analog reference signal in response to the mode signal, and a comparator configured for comparing the input signal with the reference signal selected by the multiplexer to provide the PWM control signal.

Photonic Downconversion of RF Signals With Improved Conversion Efficiency and SFDR

Abstract: A photonic microwave downconverter with improved conversion efficiency and spurious-free dynamic range (SFDR) is proposed and experimentally demonstrated based on a dual-parallel Mach–Zehnder modulator (DPMZM) and a digital signal post-processing algorithm. The radio frequency (RF) signal and the local oscillator (LO) signal are fed to the two sub-MZMs of the DPMZM, respectively, leading to an infinite isolation between the RF and LO ports. By biasing the two sub-MZMs and the parent MZM of the DPMZM at the minimum transmission point, the optical carrier can be greatly suppressed. As a result, the conversion efficiency is improved for the same power impinged on the photodetector. A preliminary experiment shows that a conversion efficiency of −12.7 dB can be achieved. On the other hand, without emulating the inverse link transfer function, where exact parameters of the photonic link should be known, a simple post-processing algorithm which just needs the modulation index of the LO signal is employed to suppress the intermodulation distortion products. The SFDR of the downconverter is improved from 101.5 dB $\cdot $ Hz $^{{2/3}}$ to 114.5 dB $\cdot $ Hz $^{{4/5}}$ by using the proposed digital linearization algorithm.

Apparatus and methods for digital signal constellation transformation

Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.

Reconfiguring paths in a multiple path analog-to-digital converter

Abstract: A method may include processing an analog input signal to generate a first digital signal in accordance with a first analog gain, processing the analog input signal to generate a second digital signal in accordance with a second analog gain, and generating a digital output signal of the processing system from one or both of the first digital signal and the second digital signal based on a magnitude of the analog input signal and setting the first analog gain based on the magnitude of the analog input when the digital output signal is generated from the second digital signal.

Imaging element, image reading device, image forming apparatus, and imaging method

Abstract: An imaging element includes: a plurality of pixel units configured to each include a plurality of light receiving elements performing photoelectric conversion; a plurality of analog-to-digital (A/D) converters configured to be provided to each of the pixel units for sequentially converting an analog signal obtained by photoelectric conversion performed by the light receiving elements to a digital signal; a plurality of first holding units configured to be provided to each of the pixel units for sequentially holding a digital signal obtained by conversion performed by the A/D converters; and a plurality of second holding units configured to receive and hold a digital signal held by the first holding units in a period when the A/D converters do not convert an analog signal to a digital signal.

Analog-to-digital converters: A comparative study and performance analysis

Abstract: Analog-to-Digital Converters (ADCs) are critical components of biomedical, communications and signal processing systems which require low power consumption and high conversion efficiency and are used to convert the real world signal to digital signal for the purpose of processing. In this paper various state-of-the-art ADC's including experimental converters, have been explored keeping in mind their application requirements. A comparative study of these ADC's, keeping in mind the various performance parameters like power consumption, resolution, sampling rate has also been presented, providing an insight into their shortcomings.

Using differential signalling to mitigate pointing errors effect in FSO communication link

Abstract: In this paper, we investigate a differential signalling (DS) scheme to mitigate pointing errors effect in intensity-modulation/direct-detection (IM/DD) free space optical (FSO) communication systems with the non-return-to-zero on-off keying (NRZ-OOK) modulation format. The most common approach to detect a digital signal is based on comparing the received signal with an optimal threshold level. Normally, this optimal threshold level is set at the mean value of the signal in a clear channel. However, this detection threshold method is inefficient in a channel with fading effects. DS has been reported to mitigate the fluctuation of optimal detection threshold in NRZ-OOK IM/DD FSO communication systems only to combat atmospheric fading effects (e.g., fog and turbulence) and to reduce the background noise of the received signal. In this paper, we adopt the DS scheme to mitigate the optimal detection threshold level fluctuations induced by pointing errors. We also discuss the conditions in which DS cancels out the fluctuation of threshold level. The proposed technique is supported by carrying out experimental investigation of the FSO link with pointing errors. Measured results confirm that the effect of PE on the received signal was highly correlated (i.e., ρ = 0.92, where ρ is the correlation coefficient between channels) thus resulting in reduced variance value of the combined signal threshold level. We also derive an expression for bit-error-rate for the system which is supported by simulation.

Alternate signaling mechanism using clock and data

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state