Digital signal

About: Digital signal is a research topic. Over the lifetime, 44213 publications have been published within this topic receiving 345279 citations.

Circuit for demodulating FSK signals

Abstract: A circuit and method of demodulating an FSK signal uses digital circuitry to convert the received signal into count values. For each reception an adaptive reference count value is determined by averaging the duration of received pulses during the preamble of the transmission. The adaptive reference count corresponds to a demodulated logic "1" or logic level "0". The counts from the coded portion of the transmission are compared to the adaptive reference count. If the count is within predetermined windows from the reference count, the count value is converted to the corresponding digital signal.

System and method for high-speed skew-insensitive multi-channel data transmission

Abstract: A method and apparatus is disclosed that receives a multi-channel digital serial encoded signal and converting it into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler ovesamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.

Digital signal routing circuit

Abstract: An integrated circuit for digital signal routing. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8 kHz or 16 kHz can be processed concurrently with audio data at 44 kHz or 48 kHz.

Multi-protocol radio frequency identification reader tranceiver

Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Electronic still camera using variable-length data compression for storing still image signals

Abstract: An image pick-up section generates an electronic still image signal. An A/D conversion section converts the electronic still image signal generated by the image pick-up section into a digital signal. A data compressing section causes variable-length encoding data compression to the digital signal obtained by the A/D conversion section so as to obtain compressed image data. A recording section records the image data compressed by the data compressing section in a recording medium having a predetermined recording capacity. A calculating section calculates an estimated count of electronic still images which can be recorded in the recording medium in accordance with quantitative data associated with the image data recorded in the recording medium by the recording section and quantitative data associated with the recording capacity of the recording medium. An indicating section indicates the estimated count of the recordable electronic still images calculated by the calculating section.