Digital signal

About: Digital signal is a research topic. Over the lifetime, 44213 publications have been published within this topic receiving 345279 citations.

Asynchronous analog-to-digital converter and method

Abstract: A method and apparatus for converting an analog input signal to a digital output signal, provide for simultaneously comparing the input signal to a sequential multiplicity of reference values representing a range of values of the input signal, and asynchronously processing digital results from simultaneous comparison to produce a digital representation of level crossings of the input signal with respect to the multiplicity of reference values.

DC offset correction scheme for wireless receivers

Abstract: A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.

Direct digital frequency synthesizer using sigma-delta techniques

Abstract: A direct digital synthesizer (DDS) for generating a waveform generates a sequence of n-bit phase signals representing phase of the waveform, wherein n is an integer greater than zero. Each n-bit phase signal comprises a phase estimate signal and a phase error signal. The phase estimate signal comprises a most-significant m bits of the n-bit quantity (0 < m < n). The phase-error signal comprises a least-significant n-m bits of the n-bit quantity. The DDS further has a sigma-delta modulator for generating a compensation signal from the phase error signals. The phase estimate signal is added to the compensation signal to produce a compensated phase signal, which may be used to address a look-up table having waveform samples stored in correspondence with look-up table addresses. A digital to analog converter may be coupled to receive wave form samples from the look-up table in order to generate a corresponding analog waveform signal. In accordance with another aspect of the invention, an improved modulator includes the improved DDS as described above, for generating a stream of carrier signal samples; and a complex multiplier/accumulator (CMAC) for multiplying a stream of the carrier signal samples by a stream of complex data values that represent a baseband signal. The output of the CMAC is a stream of modulated carrier signal samples that may be supplied to a digital to analog converter which generates a corresponding analog modulated carrier signal.

Clocked cascading current-mode regulator with high noise immunity and arbitrary phase count

Abstract: A clocked cascadable power regulator including synchronization logic and PWM control logic. The synchronization logic receives a clock signal and asserts a digital output signal synchronized with the clock signal in response to assertion of a digital input signal. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The regulator may be used alone or cascaded with other similar regulators for implementing a multiphase power converter with multiple channels. The clocked cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. In the cascaded configuration, there is one clock common to all channels which ensures that the phase separation between the channels is symmetrical to within the jitter tolerance of the common clock.

Digital in-circuit tester

Abstract: A circuit adapted for use in a high speed computer controlled digital in-circuit tester for obtaining high pulse fidelity at each electrical node of a circuit under test is provided. High pulse fidelity is obtained by minimizing the current in the power supply and digital test signal current loops for the components of the circuit under test. The tester includes a plurality of programmed memory digital test-signal generators responsive to the computer for generating and supplying to the nodes of the circuit under test a complex sequence of digital logic signals. The circuit also includes a plurality of distributed programmable power sources, each power source associated with at least one of said test signal generators, for generating the power supply voltages for the components. The power supply voltages for the components under test are obtained from the programmable power sources associated with the test signal generators involved in generating and supplying the test signals to those components, thereby localizing the component power supply current loops and the driving digital test signal current loops.