Digital signal

About: Digital signal is a research topic. Over the lifetime, 44213 publications have been published within this topic receiving 345279 citations.

Non-invasive digital communications test system

Abstract: Method and apparatus for non-invasively testing performance of a digital communication system. The test system finds particular application in digital broadcast systems where interruption of regular service for test purposes is impracticable. In one embodiment oriented to digital television cable broadcast systems, unwanted reflections due to loose connectors and other causes may be localized within a subscriber's home. The test system takes advantage of information typically generated by digital receivers to correct for communication channel imperfections. Examples of such information include current filter parameters computed for use in an internal adaptive equalizer, internal loop parameters, and the difference between the signal received and a reconstruction of that signal from the symbols estimated by the receiver.

Three input arithmetic logic unit with shifter

Abstract: A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2 N , with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Method and apparatus for coupling signals between two circuits operating in different clock domains

Abstract: A coupling circuit for coupling a first signal generated in a first circuit operating in a first clock domain to a second circuit operating in a second clock domain. The coupling circuit includes a first gate for coupling the first signal to a first logic circuit unless the coupling circuit has already applied a signal to the second circuit. The first logic circuit includes a pair of second gates that are enabled by respective rising and falling edges of the first clock signal. Thus, each of the second gates generates an output signal on respective transitions of the first clock signal as long as the first gate is coupling the first signal to the first logic circuit. The first logic circuit also includes a pair of latches coupled to respective outputs of the second gates. Each of the latches is set by its respective second gate generating the output signal. The second logic gates are coupled to a second logic circuit having a pair of third gates that are enabled by respective rising and falling edges of the second clock signal. Thus, each of the second gates generates an output signal on respective transitions of the second clock signal if the latch to which it is connected is generating an output signal. The output signal is also used as the reset signal to disable the first gate and reset the latches. Since the output signal is generated on the first transition of the first clock signal after the first signal is applied to the coupling circuit, the coupling circuit generates a single output signal that is synchronized to the second clock signal.

Systems and methods for digital detection of a tomographic signal

Abstract: Systems and methods for digital detection of an analog tomographic signal are described. The methods include receiving an amplitude-modulated analog signal containing tomographic information, the analog signal having a modulation frequency, f λi ; and converting the analog signal into a digital signal at a sampling frequency, f s , to produce a number of samples, K. The digital signal is multiplied by an in-phase reference signal to obtain an in-phase signal component, the in-phase reference signal having the frequency, fλi; and the digital signal is multiplied by a quadrature reference signal to obtain a quadrature signal component, the quadrature reference signal having the frequency, f λi . The in-phase signal component and the quadrature signal component are passed through the K-point averaging filter. A signal amplitude is computed based on the filtered in-phase signal component and the filtered quadrature signal component, the signal amplitude being representative of the tomographic information.

Analog-to-digital converting unit with broad dynamic range

Abstract: An analog-to-digital converting unit comprises an analog level varying circuit having a plurality of gains and varying a magnitude of an analog input signal for producing a plurality of analog output signals different in magnitude from one another with the respective gains, a plurality of analog-to-digital converting circuits respectively supplied with the analog output signals and producing a plurality of digital code signals, respectively, a controlling circuit supplied with two of the digital code signals and calculating a difference therebetween for producing a first control signal indicative of varying one of the digital code signals in value so as to be equal in value to the other digital code signal, a calculating circuit responsive to the first control signal and causing one of the digital code signals to be varied in value for producing a candidate of a digital output signal, and an output circuit coupled to one of the analog-to-digital converting circuits and to the calculating circuit and supplying the digital output signal to the output node. Since the value of the input analog signal is retrieved from the digital code signal on the basis of the difference, the analog-to-digital unit is free from any secular changes and any variation of operational ambient.