Showing papers on "Digital signal processing published in 1982"

Highly concurrent computing structures for matrix arithmetic and signal processing

Abstract: Computational complexity has traditionally been an important measure of the utility of digital signal processing and matrix arithmetic algorithms; however, the digital implementation of such algorithms has often been difficult (or impossible) since they tend to be computebound. Consequently, the quest for real-time processing has resulted in a concerted push for the development of faster computing structures as well as algorithms oflower computational complexity. With the advent of VLSI, many processing elements can now be realized on a single chip, and large collections of processors have therefore become economically feasible. In this article, we present the reader with several highly concurrent, pipelined computing structuresstructures that are realizable in VLSI and that exhibit large throughputs. Although the architectures we describe are introduced through the use of specific examples, they are also applicable to the solution of a variety of other problems. There are three primary reasons why general-purpose uniprocessor computers, especially microcomputers, have met with only limited success in the high-speed signal processing arena. First, they cannot, in general, efficiently compute a variety of elementary operations such as multiplication, vector rotation, and trigonometric functions; these operations are quite common im matrix arithmetic and signal processing algorithms. Second, generalpurpose computer architectures provide only cumbersome address arithmetic for data structures, such as circular buffers, that occur frequently in high-speed signal processing applications (communications, for example). And lastly, with one notable exception, signal processing algorithms exhibit a substantial amount of parallelism that is not effectively exploited in a uniprocessor system. (The exception is the AMD2900 family, which allows some parallelism through the extensive use of two-port RAMs.) Our article will primarily be concerned with architectures that exploit parallelism and that are based on powerful primitive operations. Most signal processing structures, whether parallel or not, tend to emphasize the need for fast multiplication.' However, algorithms for matrix arithmetic and signal processing call for a somewhat larger set of elementary operations: real and complex number multiplications, additions, square roots, divisions, trigonometric functions and their inverses, and, somewhat less often, hyperbolic transformations. For example, the discrete Fourier transform and the matrix decomposition via Givens' rotations demand 2 x 2 plane rotations, while matrix triangular factorization can be performed with 2 x 2 hyperbolic rotations, divisions, and square roots. Multiplications and additions are awkward to use for the generation of these general operations. However, J. E. Volder2 has introduced powerful algorithms named Cordic, for coordinate rotation digital computer, that evaluate a variety of plane coordinate transformations with iterative procedures involving only additions and shift operations at each step, In other words, Cordic processing elements are extremely simple and quite compact to realize, while being no slower than the bit serial multipliers widely proposed for VLSI array structures.3,4 Many of the more complex signal processing tasks and applications, such as statistical analysis and linear and nonlinear programming, rely on standard matrix computations. The basic problem in matrix arithmetic, for which a large number of direct and iterative schemes have been devised, is the solution of linear systems ofequations (and the closely related problem of matrix inversion). A rapid survey of direct methods of solution indicates that Givens' procedure is the method-of-choice from the VLSI implementation standpoint because it can be efficiently

Digital Low-Pass Differentiation for Biological Signal Processing

Abstract: Digital low-pass differentiation is often required in processing various biological or biomechanical data. However, both the nature of biological signals and the use of micro-or minicomputers in such applications imply the need for simple, low-order, and fast differentiation methods, rather than sophisticated high-order algorithms. Responding to this need, we investigate here the low-pass first- and second-order digital differentiation from both theoretical and practical points of view, in order to achieve good and simple algorithms. In contrast with most of the research works previously done in this field, whose main aim was to achieve better accuracy even in the cost of using quite high-order algorithms, we restrict ourselves in this study only to low orders, being interested not only in the accuracy achieved, but also in the simplicity of the algorithm. After discussing the theoretical considerations concerning our optimum low-pass differentiation filters, we present our simple low-order filters and show them to be not only very convenient for use, but also almost optimum.

Digital fundamentals

Abstract: This bestseller provides thorough, up-to-date coverage of digital fundamentals, from basic concepts to microprocessors, programmable logic, and digital signal processing. Its vivid full-color format is packed with photographs, illustrations, tables, charts, and graphs; valuable visual aids that today's user needs to understand this often complex computer application. Known for its clear, accurate explanations of theory supported by superior exercises and examples, this books full-color format is packed with the visual aids todays readers/students need to grasp often complex concepts. For those in the computer industry where a knowledge of introductory digital programming is essential.

Microcomputer system for digital signal processing

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16 x 16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0- to 15-bit shifter (S) with sign extension.

Analog and digital signal apparatus

Abstract: In order to reduce the effect of modulation of the quantizing error (noise) by the signal in an adaptive digital audio system and to increase the dynamic range of the system, the adaptive analog to digital converter is preceded by a frequency dependent network that changes the shape of its characteristic in response to a control signal. The control signal is derived from the variable scaling factor in the adaptive converter. After transmission via a transmission channel or record/playback process, complementary operations are performed by a digital to analog converter followed by a further frequency dependent variable response network.

Signal reconstruction from the short-time Fourier transform magnitude

Abstract: This paper presents various conditions that are sufficient for reconstructing a discrete-time signal from samples of its short-time Fourier transform magnitude. For applications such as speech processing, these conditions place very mild restrictions on the signal as well as the analysis window of the transform. Examples of such reconstruction for speech signals are included in the paper.

Real-Time Speech Coding

Abstract: This paper reviews our recent efforts in the design and implementation of real-time speech coders. We discuss our approach and methodology for real-time hardware for coder techniques ranging from low to high complexity. Examples of realizations are given for each approach. They include adaptive differential PCM coding, subband coding, harmonic scaling with subband coding, and adaptive transform coding. Low to medium complexity techniques are based on the use of the Bell Laboratories digital signal processing (DSP) integrated circuit. High complexity block processing techniques are based on the use of an array processing computer. We conclude with an assessment of the performance versus complexity tradeoffs involved in these coding methods.

Community antenna television arrangement for the reception and distribution of TV - and digital audio signals

Abstract: Community antenna television arrangement for the reception and distribution of TV signals and digital audio signals, in particular signals which are transmitted per satellite, including a head-end connected to a receiving antenna and a signal distribution network, a time-division multiplex signal which comprises the digital audio signals in a time-multiplex distribution, being applied to the head-end, which time-division multiplex signal is modulated on a sound carrier, the bit rate of the digital audio signals to be distributed being reduced in the head-end of the community antenna television arrangement by a TDM/FDM conversion in order to reduce signal echoes.

Apparatus for detecting pick-up at a remote telephone set

Abstract: An improved combination of a hardware and digital signal processing filter for detecting pick-up of a telephone call, solely through audio information on the telephone line, is disclosed. The apparatus employs a high gain band pass filter (28) with no automatic gain control, the output of which goes to a window comparator (30). The output from the window comparator (31) goes to a digital high pass filter (32) and from there to an integrator 37 for providing a digital output signal (40) indicative of the presence or absence on the telephone line of a signal exceeding a predetermined magnitude within the filter pass band. The digital signal is then processed by an intelligent digital filter having a set of predetermined threshold values of durations for states of the digital output signal, by which determinations of pick-up are made. The digital filter is adaptive and learns the durations high and low states of the digital output signal as they occur, subsequently checking for deviations from previously learned valid values. The digital filter includes a digital phase lock loop which will lock onto a periodic but asymmetric pattern in the digital output signal and declare pick-up when lock is lost.

A microcomputer with digital signal processing capability

Abstract: A single microcomputer for realtime digital signal processing and high-speed controller applications, with a 200ns instruction cycle, 16 × 16 parallel multiplier, 32b arithmetic unit, 144 by 16 data memory, a 1536 by 16 program and coefficient memory, will be discussed.

Automatic background noise suppressor

Abstract: A circuit for suppressing background noise of a continuous nature while enhancing speech signals, or signals having the transient temporal qualities of speech, includes a signal multiplier which, in the preferred embodiment, receives the composite audio signal along with a control signal present only when the speech component of the audio signal is present. The control signal may be derived from an AGC circuit having a slow attack, fast decay characteristic to establish a quiescent output level from the AGC amplifier in the absence of speech. An envelope detector is biased to provide a zero output amplitude in response to the quiescent amplifier output level. Speech components appearing in the amplifier output signal are then envelope-detected and filtered to provide the control signal. Alternatively, the control signal can be derived by envelope-detecting the audio signal, filtering the detected signal to remove its d.c. component representing the continuous noise, and then detecting and filtering again. In still another embodiment, the control signal acts upon a constant amplitude instead of the audio input signal in order to provide a speech-responsive tactile vibration for the deaf.

Direct digital loudspeaker

Abstract: A method of and apparatus for converting a digital signal to sound, the digital signal being encoded in a sequence of code words at a signal encoding frequency, the code words representing the analog sound pressure of an original audio signal, with decoding of the digital signal occurring after electro-acoustic transduction through mechanical rectification and characteristics of a listener's ear, includes utilizing a plurality of substantially identical sound pressure generating elements each having an individual driver associated therewith, and selectively energizing the drivers in a pulsed manner at the signal encoding frequency in combination in response to a respective order of the bits of each code word of a digital signal from a most significant bit to a least significant bit. The sum of the air pressures produced by the sound pressure generating elements in response to each of the successive code words of the digital signal has a magnitude corresponding to the analog value of the respective code word, and the auditory system of the listener has the characteristics of a low pass filter whereby the listener receives the sum of the air pressures as the analog sound pressure of the original audio signal.

Design techniques and performance of digital IFM

Abstract: The digital instantaneous-frequency-measuring receiver using delay-line discriminators was developed in the early 1960s specifically as a wideband and accurate analyser of pulsed radar signals. Various receiver configurations are incorporated in most of the more comprehensive EW systems currently in use. In the paper, the basic operating principles and design philosophy are reviewed, together with an indication of the performance presently achieveable in the field using modern MIC technology and digital signal-processing techniques. Component and operational factors affecting accuracy, sensitivity, dynamic range and band coverage are discussed. The instantaneous-frequency-following capability is assessed, including means of extracting or displaying information from frequency- or phase-modulation-on-pulse-type signals. Problems arising when multiple signals, pulse or CW, are present simultaneously can be overcome to a certain extent by using the large-signal capture effect in limiting RF preamplifiers. The degree of measurement integrity under these conditions is related to receiver design factors, and processing methods are described which can be used to identify ambiguous measurements when these occur. Finally, some practical implementations are given of digital instantaneous-frequency measurement in ESM and ECM equipments.

Toward an Intelligent Editor of Digital Audio: Signal Processing Methods

Abstract: In this article, we will describe signal processing methods that have been developed for use in an automatic music analysis system. A companion article by Chafe, Mont-Reynaud, and Rush, also in this issue of the Journal, deals with higher-level issues, namely the recognition of musical constructs. Unless one is willing to settle for a direct interface between musician and computer, such as the hardwired keyboard in the Xerox PARC system (Ornstein and Maxwell 1981), techniques must be developed to extract musical features from the sound itself. The approach of combining signal processing with knowledge engineering seems quite promising for music analysis. In contrast with many of the signals to which signal processing methods are applied, musical signals usually contain a great deal of order, chiefly in the form of quasi-periodicity (pitch and rhythm), and are not usually severely corrupted with random noise. By taking advantage of these features, one can construct mechanisms that provide musically significant descriptions of real data, such as tempo tracking ("foot-tapping"), meter analysis, attack characterization, pitch characterization (including vibrato), and timbre analysis. In this article and its companion, sample results of some promising strategies for accomplishing these goals are presented. In particular, we will concentrate on the problems of primary segmentation, that is, the first few passes through the data using little or no a priori knowledge. If we can mark the begin time for each new event in the music, the task of classifying and parameterizing each event is made easier. We have tried three approaches to this segmentation problem: (1) an amplitude thresholding method, (2) a linear predictive coding (LPC) method, and (3) a pitch detection method. While we will also discuss more advanced strategies, these are generally awaiting implementation and thus are not included in he examples.

A high-speed LSI GaAs 8x8 bit parallel multiplier

Abstract: Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.

Method and apparatus for identifying sound recordings

Abstract: In an installation comprising a master assembly for reading the sound information signals and the end-of-program sequence signals recorded on a master tape, and at least one slave assembly to record a second time the read out signals, the slave assembly comprises circuits for detecting and regenerating end-of-sequence signals, which circuits are connected to the output of the said recording amplifier, digital coding circuits by derivation from a pilot frequency for producing a coded auxiliary digital signal, means to modify the digital coding at each new detection of end-of-sequence signals and an adder circuit to add the coded auxiliary digital signal with the sound information signal before re-recording the latter.

A 2-channel, 16-bit digital sampling frequency converter for professional digital audio

Abstract: A digital sampling frequency converter for arbitrary ratios of sampling frequencies is presented. It is based on a multistage interpolating filter, and on a novel time-domain control of the filter stages by signals derived from the sampling frequency clocks. Time-domain resolution of ±300 picoseconds is obtained, compatible with digital audio of 16-bit resolution. In addition to the filter design and implementation, measurement results are presented. They indicate that 16-bit accuracy is indeed achieved, even with asynchronous, drifting and time-varying sampling frequencies. A number of applications (digital mastering, program transfer between conflicting digital audio formats, pitch control with constant sampling frequency in digital recorders, error concealment, interfaces in digital transmission) are presented.

Method and apparatus for the digital control of the phase of the system clock of a digital signal processing system

Abstract: Method for digitally controlling the phase of the system clock frequency of a digital signal processing system which processes an analog signal containing a reference signal, wherein a fixed phase relation exists between the digitalized reference signal and the system clock frequency, which includes digitalizing the reference signal by sampling the analog reference signal, weighting the scanning values of the digitalized reference signal for obtaining a digital phase comparison variable, feeding the phase comparison variable through a digital PLL filter to a digitally controlled oscillator, and deriving the system clock frequency from the output signal of the digitally controlled oscillator, and an apparatus for carrying out the method.

Digital intravenous subtraction angiography

Abstract: In a digital intravenous subtraction angiography system an X-ray generator provides low mA continuous X-ray exposures illuminating a standard image intensifier producing an image scanned by a conventional television camera to provide a video signal. An analog-to-digital converter converts the video signal into digital form. The digital frame signals are added together in real time to provide an intermediate digital signal representing the addition of typically 5 to 20 frames. A digital disk receives and stores the intermediate image signals. A subsequent intermediate image signal is added to a second memory while a previously formed intermediate image signal is transferred from a first memory to disk storage. The first and second memories are operated in "ping pong" fashion so that each and every video frame signal during the acquisition period, typically 15 seconds, is summed to form one of the intermediate images. A selected mask image signal is subtracted from any or all intermediate image signals to provide an enhanced subtracted image signal. Various mask image signals may be subtracted so that the operator may decide by visual inspection of the subtracted image signals which mask image signal minimizes misregistration artifacts. Each intermediate image signal or each subtraction intermediate image signal is weighted approximately proportional to the contrast agent intensity to form a weighted sum signal. The operator may exclude from this combining process any intermediate signal which the operator has determined is not suitably registered. An intermediate image signal may be processed to provide a phantom image signal through translation and/or rotation of the intermediate image signal.

An Analytic Signal Approach for Transmultiplexers: Theory and Design

Abstract: A new non-FFT approach to transmultiplexer implementation is presented, based on the theory of the baseband analytic signal and on its successive allocation in the FDM format by appropriate digital interpolation and filtering. The method allows wide transition bandwidths to the filters, avoids the use of any product modulator, and leads to a channel-by-channel structure. As a design example, the applicatiion to the 12-channel FDM primary group is Considered in detail, using FIR digital filters realized by 16 bit arithmetic standard digital Circuits. The analysis and the computer simulation of the system performance are finally reported, showing the actual feasibility of the method for the transmultiplexer implementation.

High-speed multiplier for microcomputer used in digital signal processing system

Abstract: A system for real-time digital signal processing employs a single-chip mircocomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. An improved multiplier circuit produces a single state 16×16 multiply function separate from the ALU, with 32-bit output to the ALU; an array of static adders with carry feed-forward controlled by two-bit-at-a-time Booth's decoders, along with a dynamic carry-ripple adder, produces the one-state 16×16 multiply. One input to the ALU passes thorugh 0-to-15 bit shifter with sign extension.

Digital to analog converter employing sigma-delta modulation for use in telephone systems

Abstract: A digital to analog converter is employed in the digital line circuit of a telephone system and operates to convert a digital signal indicative of an analog speech signal back into a replica of the analog signal. The converter operates with an interpolated input digital signal to detect by means of a sign bit, the characteristic of an input digital word as being indicative of a positive or negative level. An error correcting signal is provided by the converter which is added to the next digital word to provide a compensated word having a sign bit determined by the remainder and the sign bit of the previous digital word. This word is then processed in sequence to produce an output pulse stream from the sign detector indicative of successive positive or negative values as defined by the input digital words, each of which are modified according to the error correcting signal.

Seasat Synthetic-Aperture Radar Data Reduction Using Parallel Programmable Array Processors

Abstract: This paper presents a digital signal processing system that produces the SEASAT synthetic-aperture radar (SAR) imagery. The system consists of a SEL 32/77 host minicomputer and three AP-120B array processors. The partitioning of the SAR processing functions and the design of softwae modules is described. The rationale for selecting the parallel array processor architecture and the methodology for developing the parallel processing scheme on this system is described. This system attains a SEASAT SAR data reduction speed of 2.5 h per 25-m resolution 4-look and 100 km X 100 km image frame. A prelininary performance evaluation of this parallel processing system and potential future applications for remote sensing data reduction are described.