Showing papers on "Digital signal processing published in 1987"

Synchronous data flow

Abstract: Data flow is a natural paradigm for describing DSP applications for concurrent implementation on parallel hardware. Data flow programs for signal processing are directed graphs where each node represents a function and each arc represents a signal path. Synchronous data flow (SDF) is a special case of data flow (either atomic or large grain) in which the number of data samples produced or consumed by each node on each invocation is specified a priori. Nodes can be scheduled statically (at compile time) onto single or parallel programmable processors so the run-time overhead usually associated with data flow evaporates. Multiple sample rates within the same system are easily and naturally handled. Conditions for correctness of SDF graph are explained and scheduling algorithms are described for homogeneous parallel processors sharing memory. A preliminary SDF software system for automatically generating assembly language code for DSP microcomputers is described. Two new efficiency techniques are introduced, static buffering and an extension to SDF to efficiently implement conditionals.

Bispectrum estimation: A digital signal processing framework

Abstract: It is the purpose of this tutorial paper to place bispectrum estimation in a digital signal processing framework in order to aid engineers in grasping the utility of the available bispectrum estimation techniques, to discuss application problems that can directly benefit from the use of the bispectrum, and to motivate research in this area Three general reasons are behind the use of bispectrum in signal processing and are addressed in the paper: to extract information due to deviations from normality, to estimate the phase of parametric signals, and to detect and characterize the properties of nonlinear mechanisms that generate time series

Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing

Abstract: Large grain data flow (LGDF) programming is natural and convenient for describing digital signal processing (DSP) systems, but its runtime overhead is costly in real time or cost-sensitive applications. In some situations, designers are not willing to squander computing resources for the sake of programmer convenience. This is particularly true when the target machine is a programmable DSP chip. However, the runtime overhead inherent in most LGDF implementations is not required for most signal processing systems because such systems are mostly synchronous (in the DSP sense). Synchronous data flow (SDF) differs from traditional data flow in that the amount of data produced and consumed by a data flow node is specified a priori for each input and output. This is equivalent to specifying the relative sample rates in signal processing system. This means that the scheduling of SDF nodes need not be done at runtime, but can be done at compile time (statically), so the runtime overhead evaporates. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. This self-contained paper develops the theory necessary to statically schedule SDF programs on single or multiple processors. A class of static (compile time) scheduling algorithms is proven valid, and specific algorithms are given for scheduling SDF systems onto single or multiple processors.

Implementing the Rivest Shamir and Adleman public key encryption algorithm on a standard digital signal processor

Abstract: A description of the techniques employed at Oxford University to obtain a high speed implementation of the RSA encryption algorithm on an "off-the-shelf" digital signal processing chip. Using these techniques a two and a half second (average) encrypt time (for 512 bit exponent and modulus) was achieved on a first generation DSP (The Texas Instruments TMS 32010) and times below one second are achievable on second generation parts. Furthermore the techniques of algorithm development employed lead to a provably correct implementation.

Physically Based Simulation Model for Acoustic Sensor Robot Navigation

Abstract: A computer model is described that combines concepts from the fields of acoustics, linear system theory, and digital signal processing to simulate an acoustic sensor navigation system using time-of-flight ranging. By separating the transmitter/receiver into separate components and assuming mirror-like reflectors, closed-form solutions for the reflections from corners, edges, and walls are determined as a function of transducer size, location, and orientation. A floor plan consisting of corners, walls, and edges is efficiently encoded to indicate which of these elements contribute to a particular pulse-echo response. Sonar maps produced by transducers having different resonant frequencies and transmitted pulse waveforms can then be simulated efficiently. Examples of simulated sonar maps of two floor plans illustrate the performance of the model. Actual sonar maps are presented to verify the simulation results.

DSP-Based Testing of Analog and Mixed-Signal Circuits

Abstract: analog circuit testing university of cincinnati dsp based testing of analog and mixed signal circuits dsp based analog and mixed signal test ernet india dsp based testing of analog and mixed signal circuits dsp based testing of analog and mixed signal circuits dsp based testing of analog and mixed signal circuits mixed signal and dsp design techniques analog devices dsp-based analog and mixed-signal test combined analog/digital spectral testing for rf and dsp chapter

Direction finding localization system

Abstract: The present invention combines the relative insensitivity of the phase angle differences of a radio signal to the signal distortions inherent in an urban environment with digital signal processing techniques to produce an accurate and economical way to locate a mobile transmitter station such as a mobile telephone in a cellular telephone network. Phase angle measurements indicative of the angle of direction of a mobile transmitter station from each of a plurality of land stations are obtained by translated Hilbert transformation and are processed to produce a probability density function. The probability density functions are combined after a CHI-squared analysis to produce an area of uncertainty representing the position of the mobile transmitter station. The radio frequency signals emitted from the mobile transmitter station need have no special characteristic for the localization process. Thus, the present invention may easily work as an adjunct to an unrelated communications system such as a cellular telephone system.

The selection and application of an IIR adaptive filter for use in active sound attenuation

Abstract: The use of infinite impulse response (IIR) adaptive filters has lagged behind that of finite impulse response (FIR) adaptive filters. This has been due, in part, to the increased complexity of IIR filters and the potential for instability that exists due to the presence of poles in the transfer function. This paper discusses the use of adaptive filters for the active cancellation of acoustic noise. It is shown that IIR filters possess certain characteristics that are highly desirable for this problem. The selection of an appropriate IIR adaptive algorithm is discussed using observability considerations. It is shown that the recursive least mean square (RLMS) algorithm of Feintuch possesses significant advantages for use in a practical active attentuation system. Results are presented from computer simulations as well as an actual system using a TI TMS32010 digital signal processing microprocessor.

Coding system for reducing redundancy

Abstract: The present invention relates to methods and apparatus for processing signals to remove redundant information thereby making the signals more suitable for transfer through a limited-bandwidth medium. The present invention specifically relates to methods and apparatus useful in video compression systems. Typically, the system determines differences between the current input signals and the previous input signals using mean-square difference signals. These mean-square signals are processed and compared with one or more thresholds for determining one of several modes of operation. After processing in some mode, the processed signals are in the form of digital numbers and these digital numbers are coded, using ordered redundancy coding, and transmitted to a receiver.

Digital signal processing apparatus

Abstract: A digital signal processing apparatus having a host processor interfaced to a plurality of signal processing coprocessors through dual port memory elements is disclosed. Coprocessors represent microcoded machines wherein low level instructions directed toward the mechanics of performing a specific signal processing algorithm are contained in microcode. Thus, the host processor programs coprocessors using higher level functional instructions. Each of the coprocessors has a multiply-accumulator, a barrel shifter, an address generator, a hardware loop counter, and a microsequencer.

The IMS T800 Transputer

Abstract: The IMS T800, a complete scientific computer on a single chip, forms the basis of the most powerful supercomputer in Europe.

Pipeline interleaved programmable DSP's: Synchronous data flow programming

Abstract: In the companion paper [1], a programmable architecture for digital signal processing is proposed that requires the partitioning of a signal processing task into multiple programs that execute concurrently. In this paper, a synchronous dataflow programming method is proposed for programming this architecture, and programming examples are given. Because of its close connection with block diagrams, data flow programming is natural and convenient for describing digital signal processing (DSP) systems. Synchronous dataflow is a special case of data flow (large grain or atomic) in which the number of tokens consumed or produced each time a node is invoked is specified for each input or output of each node. A node (or block) is asynchronous if these numbers cannot be specified a priori. A program described as a synchronous data flow graph can be mapped onto parallel processors at compile time (statically), so the run time overhead usually associated With data flow implementations evaporates. Synchronous data flow is therefore an appropriate paradigm for programming high-performance real-time applications on a parallel processor like the processors in the companion paper. The sample rates can all be different, which is not true of most current data-driven digital signal processing programming methodologies. Synchronous data flow is closely related to computation graphs, a special case of Petri nets. In this paper, we outline the programming methodology by illustrating how nodes are defined, how data passed between nodes are buffered, and how a compiler can map the nodes onto parallel processors. We give an example of a typically complicated unstructured application: a voiceband data modem. For this example, using a natural partition of the program into functional blocks, the scheduler is able to use up to seven parallel processors with 100 percent utilization. Beyond seven processors, the utilization drops because the scheduler is limited by a recursive computation, the equalizer tap update loop. No attempt has been made to modify the algorithms or their description to make them better suited for parallel execution. This example, therefore, illustrates that modest amounts of concurrency can be effectively used without particular effort on the part of the programmer.

Sample rate conversion system having interpolation function

Abstract: A first digital data processing system outputs digital data obtained by sampling, in response to a clock signal of a first frequency, original data having a characteristic enabling interpolation thereof. A second digital data processing system obtaines output data by sampling input data in response to a clock signal of a second frequency. A sample rate conversion circuit receives the digital data from the first digital data processing system, converts the sample rate thereof into a sample rate suitable for the second digital data processing system, and supplies the sample rate as the input data to the second digital data processing system. The sample rate conversion circuit includes an interpolation circuit for performing interpolation of two adjacent units of data of the digital data received from the first digital data processing system, and an interpolation coefficient calculation circuit for calculating an interpolation coefficient, which is subsequently supplied to the interpolation circuit in accordance with a phase relationship between the clock signals of the first and second frequencies.

Digital direct sequence spread spectrum receiver

Abstract: A direct sequence spread spectrum receiver for receiving an RF carrier radio signal modulated with a message signal in accordance with a code having a fundamental frequency converts the received signal to an IF signal centered about a frequency f o corresponding to the code fundamental frequency offset by a Doppler shift. The IF signal is digitized and sampled at a local clock frequency to develop N-bit digital signals. Locally generated digital phase shifted sine and cosine signals at frequency f o are multiplied by a local code to obtain local 1-bit IF signals which are then correlated with the digitized IF signals to develop in phase and quadrature component signals. A tracker uses the component signals to translate the frequency of the digital local IF signal to track the Doppler shift, to maintain the local sampling frequency at 4f o , and to maintain the local code generator in synchrony with the code of the received signal. Except for the IF down conversion, the receiver employs all digital circuitry. The receiver architecture is adapted to a low power sequential tracking microreceiver.

Real-time vector excitation coding of speech at 4800 bps

Abstract: In Vector Excitation Coding (VXC), speech is represented by applying a sequence of excitation vectors to a time-varying speech production filter with each vector chosen from a codebook using a perceptually-based performance measure. Although VXC is a powerful technique for achieving natural and high quality speech compression at low bit-rates, it suffers as other excitation coders do from a very high computational complexity. Recent research has shown that codebook search computation can be reduced to approximately 40 MFlops without compromising speech quality. However, this operation count still prohibits a practical real-time implementation of the coder using today's DSP chips. We present a real-time 4.8 kb/s Pulse Excitation VXC coder (PVXC) which achieves high reconstructed speech quality and incorporates new techniques which reduce the codebook search complexity to only 0.55 MFlops. The coder utilizes an optimized excitation codebook and a promising new interframe vector predictive LPC parameter quantization scheme. A preliminary implementation using a single floating-point signal processor is described.

A silicon compiler for digital signal processing: Methodology, implementation, and applications

Abstract: This paper describes a fully integrated silicon compilation tool geared towards digital signal processing applications. The silicon compiler presented here uses a bit-serial architecture with a 1.25- µm CMOS cell library. It accepts as its input a high-level description language tailored for digital signal processing algorithms. The language supports the basic signal processing constructs such as multiplication, addition, subtraction, sample delays, logical operators, relational operators, as well as a conditional assignment. The compiler is equipped with behavioral, logic, and fault simulators, and performs placement and routing. The paper also details the use of the silicon compiler for the implementation of classical DSP algorithms: digital filters, FFT, programmable filters, as well as other more specialized applications such as adaptive algorithms and waveform synthesis. Moreover, some techniques are presented to implement more complex mathematical functions commonly used in DSP. The results of chip designs using the compiler and its impact on future designs are highlighted.

Digital image processing system and method

Abstract: A digital image processing system comprises a processor at a central, first site; and digital image processing equipment such as an analyze scanner and an expose scanner at a second site remote from the first site. The processor and the digital image processing equipment are connectable and are adapted to pass signals therebetween corresponding to signals generated by the digital image processing equipment. These signals may be representative of operator commands or digital data generated at the second site which can be monitored at the first site.

Pipeline interleaved programmable DSP's: Architecture

Abstract: Programmable processors specialized to intensive numerical computation and real-time signal processing are often deeply pipelined. The ensuing gain in throughput is moderated by the difficulty of efficiently programming such processors. Techniques for overcoming this difficulty are effective only for modest amounts of pipelining. This paper proposes applying an old but rarely used architectural approach to the design of single-chip signal processors so that the potential benefits of extensive pipelining can be fully realized. The architectural approach is to interleave multiple processes (or programs) through a single deeply pipelined processor in such a way that the disadvantages of deep pipelining disappear. Instead, the user is faced with the need to construct programs that can execute as concurrent processes. The main advantage is that much more pipelining can be used without aggravating the programming. A specific experimental architecture is outlined. The solution offered is a "system solution" in that architectural performance is considered along with programmability and ease of use. In the companion paper, data flow programming is suggested so that algorithms can be automatically partitioned for concurrent execution. Data flow provides a natural environment in which to build signal processing programs and can be supported efficiently in an architecture of the type described here.

Method and apparatus for establishing a connection in shortwave radio networks

Abstract: A connection (link setup) between individual stations of a radio network may be carried out fully automatically, and even with poor transmission quality, only the wanted stations are activated. A call signal includes a synchronization signal having narrow band, mark and space signals which form the component signals of a diverse pair of signals. A synchronization signal receiver independently detects and evaluates both of the component signals of the diverse pair as well as comparing the results thereof, with means of digital signal processing.

Active attenuation system with increased dynamic range

Abstract: An active acoustic attenuation system is provided that increases dynamic range by adjusting the amplitude of the input signal and the error signal at respective model and error inputs and providing automatic self-calibration. Input and error transducers provide analog input and error signals which are converted by an analog to digital converter to digital input and error signals for input to the model . Digital to analog converters have digital inputs from respective digital input and error signals and operate in an analog to analog mode with analog inputs from respective input and error transducers and analog outputs to the analog to digital converter . Dynamic range is also increased by adjusting the amplitude of the correction signal to the output transducer

Cardiac sense amplifier with pattern recognition capabilities

Abstract: A cardiac sense amplifier network includes a differential amplifier, a bandpass filter, a comparator network, a microprocessor, an analog-to-digital converter, and a random-access memory. The differential amplifier is responsive to incoming electrical signals containing cardiac signals and noise signals for amplifying the electrical signals and for producing amplified electrical signals. The filter is used to filter the amplified electrical signals and for producing filtered electrical signals. The comparator network compares the filtered electrical signals with first and second reference voltages and produces a flag signal indicative of when the filtered electrical signals exceed the first or second reference voltages. The microprocessor is responsive to the flag signal for initializing the same and for generating a control signal. The analog-to-digital converter is responsive to the control signal for converting the filtered electrical signals to digital data corresponding to the cardiac signals and noise signals. The random-access-memory is used to store data representative of noise signals and for storing program instructions for causing the microprocessor to subtract the noise signals from the digital data signals in order to obtain the cardiac signals which are free of noise.

The Saxpy Matrix-1: A General-Purpose Systolic Computer

Abstract: There has been no reduction in the demand for higher performance in scientific computation. This is especially true in digital signal processing because new algorithms for that application require much more computation than do conventional techniques. The increasing volumes of data from seismic surveys, sonar and radar systems, and imaging systems need to be processed; these applications are important sources of demand for more throughput. The analysis of data that are generated by such new imaging technologies as magnetic resonance imaging creates additional demand. In signal processing and scientific computing, parallelism is pervasive. While the granularity of the parallelism may vary, the opportunity to perform many calculations in parallel is characteristic of it. Harnessing this inherent, abundant parallelism through new computer architectures is now one of the major thrusts in computer technology.

The TMS320 family of digital signal processors

Abstract: This paper begins with a discussion of the characteristics of digital signal processing, which are the driving force behind the design of digital signal processors. The remainder of the paper describes the three generations of the TMS320 family of digital signal processors available from Texas Instruments. The evolution in architectural design of these processors and key features of each generation of processors are discussed. More detailed information is provided for the TMS320C25 and TMS320C30, the newest members in the family. The benefits and cost-performance tradeoffs of these processors become obvious when applied to digital signal processing applications, such as telecommunications, data communications, graphics/image processing, etc.

Data compression system and method for audio signals

Abstract: Audio signals such as ECG, speech and music are digitally processed to reduce the bit-rate needed for accurate transmission, known as minimizing the entropy of the signal. The transmitter features a digital compression filter with zeros restricted to certain points on the unit circle, and Huffman encoding for transmission. The receiver features a digital decompression filter with poles at the zero locations, but shifted inside the unit circle to prevent error-ramp build-up.

Digital hearing aids: a tutorial review.

Abstract: The basic concepts underlying digital signal processing are reviewed briefly, followed by a short historical account of the development of digital hearing aids. Key problem areas and opportunities are identified, and the various approaches used in attempting to develop a practical digital hearing aid are discussed.

A Multiprocessor Architecture for Two-Dimensional Digital Filters

Abstract: In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme, a simple interconnection network, a very high efficiency, and low data transfers and storage requirements. Thus, it avoids the bottlenecks associated with traditional parallel computers and multiprocessor systems.