Showing papers on "Digital signal processing published in 1990"

Multirate digital filters, filter banks, polyphase networks, and applications: a tutorial

Abstract: The basic concepts and building blocks in multirate digital signal processing (DSP), including the digital polyphase representation, are reviewed. Recent progress, as reported by several authors in this area, is discussed. Several applications are described, including subband coding of waveforms, voice privacy systems, integral and fractional sampling rate conversion (such as in digital audio), digital crossover networks, and multirate coding of narrowband filter coefficients. The M-band quadrature mirror filter (QMF) bank is discussed in considerable detail, including an analysis of various errors and imperfections. Recent techniques for perfect signal reconstruction in such systems are reviewed. The connection between QMF banks and other related topics, such as block digital filtering and periodically time-varying systems, is examined in a pseudo-circulant-matrix framework. Unconventional applications of the polyphase concept are discussed. >

Chapter 1 – discrete cosine transform

Abstract: Publisher Summary This chapter presents discrete cosine transform. The development of fast algorithms for efficient implementation of the discrete Fourier transform (DFT) by Cooley and Tukey in 1965 has led to phenomenal growth in its applications in digital signal processing (DSP). The discovery of the discrete cosine transform (DCT) in 1974 has provided a significant impact in the DSP field. While the original DCT algorithm is based on the FFT, a real arithmetic and recursive algorithm, developed by Chen, Smith, and Fralick in 1977, was the major breakthrough in the efficient implementation of the DCT. A less well-known but equally efficient algorithm was developed by Corrington. Subsequently, other algorithms, such as the decimation-in-time (DIT),decimation-in-frequency (DIF), split radix, DCT via other discrete transforms such as the discrete Hartley transform (DHT) or the Walsh-Hadamard transform (WHT), prime factor algorithm (PFA), a fast recursive algorithm, and planar rotations, which concentrate on reducing the computational complexity and/or improving the structural simplicity, have been developed. The dramatic development of DCT-based DSP is by no means an accident.

Analog & digital signal processing

Abstract: The Fourier series in spectral analysis and function approximation the Fourier transformation and generalized signals the Laplace transformation and some of its applications analogue signal processing systems digitization of analogue signals discrete signals and systems design of digital filters the fast fourier transform and its applications stochastic signals and power spectra finite word-length effects in digital signal processors linear estimation and adaptive filtering.

Electronic still camera utilizing image compression and digital storage.

Abstract: An electronic still camera employs digital processing of image signals corresponding to a still image and storage of the processed image signals in a removable static random access memory card (24). An image sensor (12) is exposed to image light and the resultant analog image information is converted to digital image signals. A control processor (20) controls the exposure section (10) and an A/D converter (16), delivering digital signals to a multi-image buffer (18) at a rate commensurate with normal operation of the camera. A digital processor (22) operates on the stored digital signals, transforming blocks of the digital signals and encoding the signals into a compressed stream of processed image signals, which are downloaded to the memory card. The digital processor (22) operates at a throughput rate different than the input rate for better image capture and optimum utilization of the camera.

Characterization of single channel currents using digital signal processing techniques based on Hidden Markov Models.

Abstract: Techniques for extracting small, single channel ion currents from background noise are described and tested. It is assumed that single channel currents are generated by a first-order, finite-state, discrete-time, Markov process to which is added `white' background noise from the recording apparatus (electrode, amplifiers, etc.). Given the observations and the statistics of the background noise, the techniques described here yield a posteriori estimates of the most likely signal statistics, including the Markov model state transition probabilities, duration (open- and closed-time) probabilities, histograms, signal levels, and the most likely state sequence. Using variations of several algorithms previously developed for solving digital estimation problems, we have demonstrated that: (1) artificial, small, first-order, finite-state, Markov model signals embedded in simulated noise can be extracted with a high degree of accuracy, (2) processing can detect signals that do not conform to a first-order Markov model but the method is less accurate when the background noise is not white, and (3) the techniques can be used to extract from the baseline noise single channel currents in neuronal membranes. Some studies have been included to test the validity of assuming a first-order Markov model for biological signals. This method can be used to obtain directly from digitized data, channel characteristics such as amplitude distributions, transition matrices and open- and closed-time durations.

Automatic image stabilizing system by full-digital signal processing

Abstract: An automatic image-stabilizing system for camcorders and VCRs utilizing only digital signal processing has been developed New technologies for this system are (1) the BERP (band extract representative point) matching technique with a small-scale circuit, (2) an adaptive system control algorithm to discriminate moving objects, and (3) suppression of motion vectors due to noise Calculations show that the motion vector detector requires only 11000 gates, the electronic zoom controller requires only 8500 gates, and only one 8-b field memory is required >

Arc hitecture-Driven Synthesis Techniques for VLSl Implementation of DSP Algorithms

Abstract: Digital signal processing (DSP) is a rapidly growing discipline as VLSl technology makes real-time digital algorithms for speech, audio, image processing, video, and control systems economically feasible. Due to the competitiveness of the application field, cutting design time is a key issue for DSP. Silicon compilation is a way to achieve this. In this paper the state of the art of compiling DSP algorithms into silicon is discussed. First it is indicated how digital signal processing differs from numerical data processing, including the consequences on the synthesis tools. Unlike compilers generating general-purpose microprocessors, DSP synthesis requires tools for analysis, optimization and simulation of the bittrue behavior of the algorithm at the highest level. An applicative input language for specifying the behavior of DSP systems is advocated. Based on a wide span of DSP applications, four classes of architectures are distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioural DSP specification. The four selected architectural styles are best characterized by the following keywords: hard-wired bitserial data-paths, microcoded multiprocessors, cooperating bitparallel data-paths and, finally, regular arrays. Each of the CATHEDRAL compilers is based on a mixture of knowledge-based architecture generation techniques and algorithmic optimizations. Silicon is generated from technology-updatable libraries of primitive cells, by means of structured module-generators or by using a standard-cell design system. Attention is paid to the assembly of test patterns for the synthesized chips. The CATHEDRAL programs support interactive synthesis for the four abovementioned architectures, all the way from the applicative bit-true specification to silicon. For each compiler the design trajectory starting from a high-level specification down to layout is analyzed in the paper. Each of the CArHEDRALs and their underlying methodology is illustrated with the complete design of a representative example.

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms

Abstract: The state of the art of compiling digital signal processing (DSP) algorithms into silicon is discussed. It is indicated how digital signal processing differs from numerical data processing, including the consequences for the synthesis tools. On the basis of a broad range of DSP applications, four classes of architectures are then distinguished to serve as templates for four different synthesis systems. Although each of these four silicon compilers is tuned to a specific class of applications in order to generate area-efficient chips, they all accept as input the same behavioral DSP specification. The four selected architectural styles are best characterized by hard-wired bit-serial data-paths, microcoded multiprocessors, cooperating bit-parallel data-paths, and regular arrays. The characteristics of the first three architectures are treated in more detail in a discussion of three different Cathedral synthesis environments for their respective design. A fourth Cathedral environment, aiming at the synthesis of regular arrays, is still in an early stage of development and is not discussed. The claims for the compilers are substantiated by typical designs. >

Radio frequency receiver for a NMR instrument

Abstract: A receiver processes an NMR signal to produce a baseband image information signal from which two quadrature component signals are derived. An intermediate frequency section mixes the received NMR signal with two reference signals to shift the image information into a frequency band having a bandwidth BW and centered at a frequency that is 1.5 times the bandwidth BW. The resultant signal is filtered to remove extraneous signals outside the image information band. An analog to digital converter samples the filtered signal at a rate that is twice the bandwidth BW and digitizes the samples into a digital signal. A quadrature detector derives I and Q output signals from the digital signal by alternately selecting digital samples and negating every other sample selected for each of the I and Q output signals. The quadature detector also digitally filters the I and Q signals which are then used to construct an NMR image.

System transmitting and receiving digital and analog information for use in locating concealed conductors

Abstract: An improved locator system is provided which transmits digital and analog information over an electromagnetic field that is radiating from an underground source. The locator system includes a transmitter that modulates its output signal by turning its output signal on and off in response to a sequence of digital words. The transmitter also modulates an analog signal onto the transmitted signal. The modulated analog signal can include an audio frequency or voice signal. The improved locator system also includes a receiver that senses and detects the transmitted digital or analog signal impressed on the radiated electromagnetic field. The receiver also demodulates the transmitted audio frequency signal and provides an audio output signal to an operator.

Multiplier policies for digital signal processing

Abstract: The successful design of digital signal processing (DSP) systems and subsystems is often predicated on realizing fast multiplication in digital hardware. This tutorial provides the reader with a broad perspective of this important field and the pedagogy needed to understand the basic principles of digital multiplication. Both conventional and nonconventional methods of implementing multiplication, representing a mix of speed/complexity tradeoffs, are presented. Some are based on traditional shift-add structures, whereas others strive for greater mathematical sophistication. Topics include stand-alone fixed-point multipliers, cellular arrays, memory intensive policies, homomorphic systems, and modular arithmetic. >

Analog and Digital Signal Processing

Abstract: From the Publisher: Provides well balanced, detailed coverage of the techniques of signal processing in both the analog and digital domains and the ways in which they are linked in practical applications. Topics include spectral analysis of continuous and discrete signals, analysis of continuous and discrete systems and networks using transform methods, design of analog and digital filters, digitization of analog signals, power spectrum estimation of stochastic signals, the fast Fourier transform algorithms, finite word-length effects in digital signal processors and linear estimation and adaptive filtering.

Programmable hybrid hearing aid with digital signal processing

Abstract: Programmable hybrid hearing aid with digital signal processing comprising a main section (1) which can be inserted in the meatus (6). The main section (1) comprises an open connection between the ear opening and an inner portion of the meatus (6), providing an acoustic transmission channel with low-pass characteristic and resonant amplification. The main section further comprises an electroacoustic transmission channel based on digital signal processing and a signal processor (DSP) and with possibility for suppressing a possible acoustic signal feedback through the acoustic transmission channel. A variant of the hearing aid is provided with a microphone (M1) and the feedback signal is suppressed by digital filtering. Another variant of the hearing aid employs two microphones (M1.M2). and the feedback signal may then be suppressed by phasing out before the digital signal processing, while the digital signal processing also comprises cancellation of the feedback signal in case of high gain. A number of response functions are stored in a memory (RAM2) in a control unit and is freely chosen by the user in regard of adaption to hearing function and acoustic environment. All the electronics of the electroacoustic channel in the hearing aid is implemented as a monolithic integrated circuit (3) in CMOS technology.

Modular digital signal processing system

Abstract: A modular digital signal processor system for calculating "wavelet-analysis transformations" and "wavelet-synthesis transformations" of one-dimensional numerical data and multi-dimensional numerical data for solving speech processing and other problems. The system includes one or more "dual-convolver" components, "analyzer-adjunct" components, "synthesizer-adjunct" components, "de-interleaver components" and "interleaver components", and specific configurations of these components for implementing specific functions. Each dual-convolver is capable of loading a finite number of numerical values into its coefficient registers and subsequently performing two convolution operations on input sequences of numerical values to produce an output sequence of numerical values. Two dual-convolvers are configured with an analyzer adjunct or synthesizer adjunct to respectively build a single stage analyzer or synthesizer. Analyzers and synthesizers are configured in conjunction with interleavers and de-interleaver components to build wavelet sub-band processors capable of decomposing one-dimensional sequences of numerical data or multi-dimensional arrays of numerical data into constituent wavelets and to synthesize the original sequences or arrays from their constituent wavelets. Synthesizers are configured with interleavers to build function generators capable of calculating functions including wavelet functions to within any specified degree of detail.

Method and apparatus for digitally processing a high definition television augmentation signal

Abstract: A method and apparatus for digital encoding are described for compressing the augmentation channel signals (chrominance and luminance signals for panel information and high frequency luminance and line difference signal) so that this information can be transmitted in a 3 MHz wide RF channel using a digital transmission scheme such as QPSK. Analog signal components are sampled and converted to digital signals. Each of the signals is fed into a separate coder which reduces the number of bits/pixel required to reconstruct the original signal. Compression is achieved by quantization and removal of redundancy. The compression scheme is based on the use of DCT together with VLC. Each augmentation signal has its own coder, which is adapted to the unique statistics of this signal.

A fully-asynchronous digital signal processor using self-timed circuits

Abstract: Self-timed circuits with an appropriate handshake protocol can be used to eliminate the requirement for a global clock in a system. At the board level, asynchronous interfaces already make use of this approach. The natural extension of this concept is to use the same communication between blocks within an IC. To demonstrate this approach, self-timed circuits, or circuits which generate a completion signal, were used, along with interconnection circuits, following a four-cycle handshaking protocol, to design and fabricate a complete general-purpose digital signal processor (DSP). Internally, stages communicate at their own speed, which is an advantage because the speed of operation no longer is constrained by the slowest block in the system. The design methodology becomes modular, the blocks being decoupled with respect to their timing considerations. The DSP contains a full data path, with several feedback paths requiring synchronization between words at different stages of the pipe. Self-timed circuits are used throughout and all communication follows a handshaking protocol. >

An introduction to speech and speaker recognition

Abstract: Five approaches that can be used to control and simplify the speech recognition task are examined. They entail the use of isolated words, speaker-dependent systems, limited vocabulary size, a tightly constrained grammar, and quiet and controlled environmental conditions. The five components of a speech recognition system are described: a speech capture device, a digital signal processing module, preprocessed signal storage, reference speech patterns, and a pattern-matching algorithm. Current speech recognition systems are reviewed and categorized. Speaker recognition approaches and systems are also discussed. >

Dsp based radio with diminished power requirements

Abstract: A radio (100) having two signal processing paths, one including a digital signal processor (104) that consumes a relatively large amount of power and one including a signal processor (106) that consumes a relatively small amount of power. The low power processor (106) operates to monitor for broadcast signals of interest. Upon detecting such a signal, the low power processor (106) enables the digital signal processor (104) to facilitate proper signal processing.

Broadcast digital sound processing system

Abstract: A broadcast digital sound processing system includes an ISA (Industry Standard Architecture) bus compatible personal computer with a hard disk drove and a sound processor board installed in an expansion slot of the computer. The board includes a stereo input, analog to digital converter (ADC) and a stereo set of digital to analog converters (DAC's) interfaced to a digital signal processor (DSP) chip. A stereophonic audio signal is converted to digital data by the ADC and communicated to the computer by the DSP chip through a two port record first-in/first-out (FIFO) buffer for storage on the disk. A program is played back by communicating a program data file through a two port playback FIFO buffer to the DSP and from there to the DAC's for reconstruction to a stereo set of analog signals. The reconstructed audio signals may then be used as a modulating signal for radio broadcasting.

An efficient microcode compiler for application specific DSP processors

Abstract: A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented. >

Extending the notion of a window system to audio

Abstract: With audio's increasing importance in computer applications, users will soon need presentation, management and organizational capabilities similar to visual window systems to avoid a confusing cacophony of multiple audio sources sounding at once. The ways in which an audio window system could be used are described. These include multimedia documents, spatial data management systems, and teleconferencing. The signal processing methods used to create hierarchical and spatial distribution among nearly arbitrary (not pure sine wave) audio sources are discussed. A prototype system, combining hierarchical and spatial processing functions with a computer-controlled switch, software and human input devices, is presented. Two envisioned implementations, a terminal-based system and a network-based server, are described. Preliminary work suggests that an effective audio window system needs much less complexity and fewer levels of digital signal processing precision than the current prototype. >

Low-overhead symbol timing and carrier recovery for TDMA portable radio systems

Abstract: Simulation and experimental results for a hardware implementation of a low-overhead digital coherent burst demodulator for time-division multiple-access (TDMA) radio systems using short bursts are analyzed. This implementation is based on digitizing a receiving signal after a low-frequency IF amplifier and performing all demodulation functions using digital signal processing techniques. Demodulation with very low overhead for TDMA is made possible by storing a burst in memory. A novel forward loop plus backward loop structure performs carrier recovery. Symbol-timing and carrier-frequency-offset estimations are performed by block processes, using the error signal resulting from differential demodulation. Bursts as short as 32 symbols can be demodulated without overhead. Since the demodulator is entirely digital and has the potential for low-power VLSI implementation, it is suitable for a portable radio system. Other advantages of this implementation include the availability of a channel quality measure derived from symbol timing estimation and the possibility of providing differential detection when it is desirable. >

GRAPE: a CASE tool for digital signal parallel processing

Abstract: The use of computer-aided software engineering (CASE) tools for stream-oriented real-time digital signal processing (DSP) applications is discussed. These applications are characterized by a continuous stream of data samples or a continuous stream of blocks of data samples arriving at the processing facility at time instances completely determined by the outside world. An overview of existing development tools for DSP is given. The CASE tool GRAPE (graphical programming environment), which allows for easy programming, compiling, debugging and evaluating of high-frequency real-time DSP systems, is presented. Its main distinctive feature is that the tool spans the whole design process, ranging from analysis over simulation and emulation up to implementation on general-purpose DSP multiprocessors or integration on an application-specific integrated circuit (ASIC). The DSP multiprocessor can be the target hardware or can be used for real-time emulation or accelerated simulation of an ASIC. >

Real-time integration and differentiation of analog signals by means of digital filtering

Abstract: The performance of digital infinite impulse response (IIR) integrators and differentiators, calculated by means of a maximum likelihood estimator for transfer functions, is compared with that of their finite impulse response (FIR) counterparts and that of classical numerical integration and differentiation. An original design method that generates stable and reduced-order IIR filters in the complex domain (amplitude as well as phase constraints) is presented. In contrast to common opinion, it is shown that it is possible to design easy realizable IIR integrators and differentiators with an arbitrary small amplitude and phase error. Although there is no FIR alternative for IIR integrators, both FIR and IIR methods give competitive results for differentiators. It is shown that, owing to the design of pure delay filters, the (optimal) fractional delay integrators and differentiators can be used in case the original waveform and one (or more) of its (higher order) derivatives and (or) integrals are required. >

Hypercomplex numbers in digital signal processing

Abstract: A new number system, reduced biquaternions (RBs), is introduced. They are related to the quaternions and biquaternions proposed by W.R. Hamilton (1969). It is shown that a further reduction of systems degree will occur if RBs are used. An example shows the realization of a fourth-order real filter by means of a first-order RB filter. With the introduction of the RBs a new method is obtained for the design of wave digital Hilbert transformers. >

Signal processing device and method

Abstract: A signal processing device for generating an output signal corresponding to a multi-dimensional input signal such as a two-dimensional image and a method of processing such a signal. The device includes an array of processing elements which are congruent and shaped so that they can be arranged on a processing element so that adjacent pairs of elements considered as a unit are geometrically similar to each processing element. Output signals of individual processing units are linearly ordered in such a manner as to maintain adjacency of signals from adjacent processing elements in the array. The ordering facilitates one-dimensional Haar transform processing of the signals in such as a manner as to localize signal energy.

Integrated digital signal processor/general purpose CPU with shared internal memory

Abstract: An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected by the general purpose processor. The general purpose processor processes the digital data recovered by the DSP module, but is also available to perform general purpose tasks. A shared internal memory array selectively provides information to the DSP module and to the general purpose processor. The information stored in the internal memory array includes operands utilized in the execution of the DSP algorithm and selected instructions and data utilized by the general purpose CPU either for controlling the execution of the DSP algorithm or for executing its own general purpose tasks. While in many applications the data processing system will include an analog front end that converts a modulated input signal received on an analog transmission channel to a corresponding digital signal for processing by the data processing system, the data processing system may also receive the digital signal directly from a digital source.

The linc transmitter

Abstract: A technique for producing linear amplification of a bandpass signal using both non-linear components and digital signal processing is the subject of this article With this technique the bandpass signal is decomposed into two constant-amplitude phase modulated signals These two phase modulated signals can be nonlinearily amplified and passively recombined to produce a linearly amplified signal

A Kalman filter based digital percentage differential and ground fault relay for a 3-phase power transformer

Abstract: The design and real-time implementation of a Kalman-filter-based digital percentage differential and a ground-fault protection scheme for three-phase power transformers are presented. A set of eleven-state Kalman filters is used to estimate the fundamental and up to fifth harmonic components of the transformer current signals. The protective relay is equipped with an even harmonic restraint during magnetizing inrush conditions and a fifth harmonic restraint during overexcitation conditions. The restraint during external faults is provided by means of a percentage differential characteristic. The relay operates in half a cycle during internal faults. In order to achieve sensitive ground-fault protection, separate primary and secondary ground-fault protection are provided. The relay algorithm is implemented on a single TMS320 digital signal processor and tested in real time using a three-phase laboratory power transformer. >