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Showing papers on "Digital signal processing published in 1992"


Book
01 Jan 1992
TL;DR: This paper presents a meta-analysis of the Z-Transform and its application to the Analysis of LTI Systems, and its properties and applications, as well as some of the algorithms used in this analysis.
Abstract: 1. Introduction. 2. Discrete-Time Signals and Systems. 3. The Z-Transform and Its Application to the Analysis of LTI Systems. 4. Frequency Analysis of Signals and Systems. 5. The Discrete Fourier Transform: Its Properties and Applications. 6. Efficient Computation of the DFT: Fast Fourier Transform Algorithms. 7. Implementation of Discrete-Time Systems. 8. Design of Digital Filters. 9. Sampling and Reconstruction of Signals. 10. Multirate Digital Signal Processing. 11. Linear Prediction and Optimum Linear Filters. 12. Power Spectrum Estimation. Appendix A. Random Signals, Correlation Functions, and Power Spectra. Appendix B. Random Numbers Generators. Appendix C. Tables of Transition Coefficients for the Design of Linear-Phase FIR Filters. Appendix D. List of MATLAB Functions. References and Bibliography. Index.

3,911 citations


Journal ArticleDOI
TL;DR: This paper presents the derivation of these narrow correlator spacing improvements, verified by simulated and tested performance.
Abstract: Historically, conventional GPS receivers have used 1.0 chip early-late correlator spacing in the implementation of delay lock loop s (DLLs), However, there are distinct advantages to narrowing this spacing, especially in C/A-code tracking applications. These advantages are the reduction of tracking errors in the presence of both noise and multipath. The primary disadvantage i s that a wider precorrelation bandwidth is required, coupled with higher sample rates and higher digital signal processing rates. However, with current CMOS technology, this is easily achievable and well worth the price. Noise reduction is achieved with narrower spacing because the noise components of the early and late signals are correlated and ten d to cancel, provided that early and late processing are simultaneous (not dithered). Multipath effects are reduced because the DLL discriminator is less distorted by the delayed multipath signal. This paper presents the derivation of these narrow correlator spacing improvements, verified by simulated and tested performance.

749 citations


Journal ArticleDOI
TL;DR: In this paper, the evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, is reviewed.
Abstract: The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms. >

492 citations


Journal ArticleDOI
01 Feb 1992
TL;DR: An attempt is made to organize and survey recent work, and to present it in a unified and accessible form, on the need for a new approach suitable for high-speed processing and the use of difference operators in numerical analysis.
Abstract: An attempt is made to organize and survey recent work, and to present it in a unified and accessible form. The need for a new approach suitable for high-speed processing is discussed in the context of several applications in control and communications, and a historical perspective of the use of difference operators in numerical analysis is presented. The general systems calculus, based on divided-different operators is introduced to unify the continuous-time and discrete-time systems theories. This calculus is then used as a framework to treat the three problems of system state estimation; system identification and time-series modeling; and control system design. Realization aspects of algorithms based on the difference operator representation, including such issues as coefficient rounding and implementation with standard hardware, are also discussed. >

276 citations


Book
01 Jan 1992
TL;DR: In this article, the authors proposed a method to solve the problem of "uniformity" in the literature. But, the method was ineffective. And, also, incomplete.
Abstract: Outline:

233 citations


Patent
29 May 1992
TL;DR: In this paper, a video digital signal processing and display system that allows real-time processing of video images with extensive filtering and inter-pixel interpolation is presented, which includes a front end user and program interface supported by a personal computer.
Abstract: A video digital signal processing and display system that allows real time processing of video images with extensive filtering and inter-pixel interpolation. The system includes a front end user and program interface supported by a personal computer, and also includes a microprocessor for controlling the system and specialized video circuitry including an image translator. The image translator performs image translation, perspective projection, scaling, rotation, border insertion, and formation of composite images. The image translator interacts with the other specialized video circuitry which includes a frame constructor, a keyer and crosspoint switches, and a frame store constructor.

218 citations


Journal ArticleDOI
TL;DR: The structure and performance of a real-time digital simulator (RTDS) for testing relays are described and examples are given of tests on a commercial distance relay.
Abstract: The structure and performance of a real-time digital simulator (RTDS) for testing relays are described. The RTDS uses parallel processing architecture based on a state-of-the-art digital signal processor (DSP) to run power system simulations in real time with a time step of 50-100 mu s. Physical devices such as relays, energy monitors for MOVs, or power system stabilizers can be fed with the appropriate signals from the RTDS and the output from the physical device can be fed back into the simulation. Examples are given of tests on a commercial distance relay. >

210 citations


Patent
24 Nov 1992
TL;DR: In this paper, a digital communication system using superposed transmission of high and low speed digital signals capable of transmitting superposed high-and low-speed digital signals through an identical frequency band was proposed.
Abstract: A digital communication system using superposed transmission of high and low speed digital signals capable of transmitting superposed high and low speed digital signals through an identical frequency band efficiently by increasing a simultaneously transmittable number of channels in the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals. In this system, the low speed digital signals are transmitted in a form of spread spectrum signals and the high speed digital signals are cancelled out from the superposed transmission signals in obtaining the output low speed digital signals by using the phase inverted replica of the high speed digital signals to be combined with the superposed transmission signals, so that it becomes possible to increase a number of channels for the low speed digital signals, while achieving the practically reasonable bit error rate performances for both the high speed digital signals and the low speed digital signals.

206 citations


Proceedings ArticleDOI
23 Mar 1992
TL;DR: A variety of signal processing issues associated with the analysis and synthesis of chaotic signals are outlined and two examples are described in detail, illustrating some possible ways in which the characteristics of chaos signals and systems can be exploited.
Abstract: Signals generated by chaotic systems represent a potentially rich class of signals both for detecting and characterizing physical phenomena and in synthesizing new classes of signals for communications, remote sensing, and a variety of other signal processing applications. Since classical techniques for signal analysis do not exploit the particular structure of chaotic signals there is both a significant challenge and an opportunity in exploring new classes of algorithms matched to chaotic signals. The authors outline a variety of signal processing issues associated with the analysis and synthesis of chaotic signals. In addition two examples are described in detail, illustrating some possible ways in which the characteristics of chaotic signals and systems can be exploited. One example is a binary signaling scheme using chaotic signals. The second example is the use of synchronized chaotic systems for signal masking and recovery. >

200 citations


Journal ArticleDOI
TL;DR: A field-programmable multiprocessor integrated circuit, PADDI, has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications.
Abstract: A field-programmable multiprocessor integrated circuit, PADDI (programmable arithmetic devices for high-speed digital signal processing), has been designed for the rapid prototyping of high-speed data paths typical to real-time digital signal processing applications. The processor architecture addresses the key requirements of these data paths: (a) fast, concurrently operating, multiple arithmetic units, (b) conflict-free data routing, (c) moderate hardware multiplexing (of the arithmetic units), (d) minimal branch penalty between loop iterations, (e) wide instruction bandwidth, and (f) wide I/O bandwidth. The initial version contains eight processors connected via a dynamically controlled crossbar switch, and has a die size of 8.9*9.5 mm in a 1.2- mu m CMOS technology. With a maximum clock rate of 25 MHz, it can support a computation rate of 200 MIPS and can sustain a data I/O bandwidth of 400 Mbytes/s with a typical power consumption of 0.45 W. An assembler and simulator have been developed to facilitate programming and testing of the chip. >

190 citations


Journal ArticleDOI
TL;DR: An introduction to digital filtering is offered here to foster the explicit design and use of digital filters and to clarify basic concepts important to both analog and digital filtering.
Abstract: Digital filtering offers more to psychophysiologists than is commonly appreciated. An introduction is offered here to foster the explicit design and use of digital filters. Because of considerable confusion in the literature about terminology important to both analog and digital filtering, basic concepts are reviewed and clarified. Because some time series concepts are fundamental to digital filtering, these are also presented. Examples of filters commonly used in psychophysiology are given, and procedures are presented for the design and use of one type of digital filter. Properties of some types of digital filters are described, and the relative advantages of simple analog and digital filters are discussed.

Book
01 Jan 1992
TL;DR: Providing comprehensive coverage of signal processing randomization techniques, this book reveals how these methods open up new possibilities in the field, and considerably widen the application areas of digital signal processing.
Abstract: Providing comprehensive coverage of signal processing randomization techniques, this book reveals how these methods open up new possibilities in the field, and considerably widen the application areas of digital signal processing. Gives new insight into traditional DSP theory.

Patent
04 May 1992
TL;DR: In this article, a single notch filter is used to remove the carrier frequency from the voice signal at the receiving end, which is then combined with the digital signal by combining to produce a composite analog signal that is transmitted to a receiving end.
Abstract: At a transmitting end, frequencies used to a construct a digital signal are substantially removed from an analog signal by a notch filter circuit to produce an interim signal which is then combined with the digital signal as by combining to produce a composite analog signal that is transmitted to a receiving end. At the receiving end the frequencies used to construct the digital signal are substantially removed from the composite analog signal by a notch filter circuit. In this way the digital signal can be transmitted simultaneously with the analog signal without errors that could be introduced by the analog signal, and with only a slight change to the frequency spectrum of the analog signal. This can be used in telephone communications for sending caller ID digital data over the same line carrying a voice signal. Caller ID data is sent FSK encoded and only those frequency used for the mark and the space are attenuated in the received voice signal before it reaches the telephone's speech circuit. For PSK encoded data method, a single notch filter removes the carrier frequency from the voice signal at the receiving end. In this way, the user is not subjected to the audible frequencies used to transmit the caller ID data, but the overall fidelity of the voice signal is only insignificantly reduced.

Journal ArticleDOI
TL;DR: In this paper, a numerical tool commonly used in digital signal processing, the exponential window method, is briefly reviewed and applied to problems in structural dynamics, which allows one to carry out analyses of undamped structures in the frequency domain, and yields highly accurate results for both discrete and continuous systems.
Abstract: A numerical tool commonly used in digital signal processing, the exponential window method, is briefly reviewed in this paper and applied to problems in structural dynamics. This method allows one to carry out analyses of undamped structures in the frequency domain, and yields highly accurate results for both discrete and continuous systems. In essence, the solution involves: (1) Finding both the transfer function and the forward Fourier transform of the excitation for complex frequencies; (2) performing a standard inverse Fourier transformation into the time domain; and (3) removing the effect of the complex frequencies by means of an exponential factor (or window). Excellent results are obtained when this factor is chosen so that the power of the excitation and response signals at the end of the window are attenuated by some three orders of magnitude. In such case, it is found that a quiet zone (a tail of trailing zeroes) is not needed for accurate computations, and that temporal aliasing (folding) is n...

Journal ArticleDOI
TL;DR: Several important digital processing techniques for optical-fiber sensor systems that use electronically scanned white-light interferometry are presented, which are able to increase greatly the dynamic range of the measurement under a low signal-to-noise ratio environment.
Abstract: Several important digital processing techniques for optical-fiber sensor systems that use electronically scanned white-light interferometry are presented. These include fringe restoration, fringe-order identification, and resolution enhancement techniques. A pure low-coherence interference fringe pattern is restored by dividing, pixel by pixel, the beam intensity profile from the signal. The central (zero-order) fringe of the pattern is identified by using a centroid algorithm. A linear interpolation or a localized centroid algorithm is used to enhance further the phase resolution. Theoretical analyses, computer simulations, and experimental verifications have shown that these techniques are able to increase greatly the dynamic range of the measurement under a low signal-to-noise ratio environment.

Book ChapterDOI
01 Jan 1992
TL;DR: This paper presents a tutorial overview of multirate digital signal processing as applied to systems for decimation and interpolation, and discusses a theoretical model for such systems (based on the sampling theorem) and how various structures can be derived to provide efficient implementations of these systems.
Abstract: The concepts of digital signal processing are playing an increasingly important role in the area of multirate signal processing, i.e, signal processing algorithms that involve more than one sampling rate. In this paper we present a tutorial overview of multirate digital signal processing as applied to systems for decimation and interpolation. We first discuss a theoretical model for such systems (based on the sampling theorem) and then show how various structures can be derived to provide efficient implementations of these systems. Design techniques for the linear-time-invariant components of these systems (the digital filter) are discussed, and finally the ideas behind multistage implementations for increased efficiency are presented.

Patent
28 Feb 1992
TL;DR: In this article, a global positioning system receiver method and system which converts the analog signals to digital signals prior to performinng signal acquisition and GPS unique processing functions is disclosed, which allows full multi channel tracking with several channels (202, 203, 204) each tracking a separate signal while the remainder of the channels rove over all of the signals on the alternate L-band with programmable duty cycles.
Abstract: There is disclosed a global positioning system receiver method and system which converts the analog signals to digital signals prior to performinng signal acquisition and GPS unique processing functions. The A/D converter (201) uses full null zone processing to increase anti-jamming capability and 4-level output to reduce signal processing. A. single analog and digital channel (302) is used for both the L1 and L2 channels as well as for all P(Y)-code and C/A-code thus allowing full multi channel tracking with several channels (202, 203, 204) each tracking a separate signal while the remainder of the channels rove over all of the signals on the alternate L-band with programmable duty cycles. The system allows for Y-code substitution for P-code by multiplexing a portion of the Y-code generated between multiple channels.

Patent
09 Jan 1992
TL;DR: A decoder for recovering an analog signal from its digital representation produced by an encoder employing adaptive-delta-modulation first decodes audio bit-stream (17) in the digital domain with digital delta demodulation (15), to a pulse-codemodulation (PCM) format digital signal.
Abstract: A decoder for recovering an analog signal from its digital representation produced by an encoder employing adaptive-delta-modulation first decodes audio bit-stream (17) in the digital domain with digital delta demodulation (15), to a pulse-code-modulation (PCM) format digital signal. Post-processing (35), complementary to encoder processing is performed digitally on the PCM signal. The output from post-processor (35) is up-sampled, and using delta modulation, a noise shaped single-bit highly oversampled output is produced by converter (14). Applying the single-bit output to lowpass filter (11) re-constructs the decoded analog signal, which is audio output (12). By fully exploiting digital signal processing techniques, the decoder can be manufactured at low cost and exceed the performance of existing analog implementations.

Patent
05 Oct 1992
TL;DR: In this article, a digital signal processing (DSP) radio receiver employs a conventional analog RF tuner to produce an analog intermediate frequency, and performs DSP functions of digitally sampling the analog intermediate frequencies at a sampling rate fs, concurrently mixing, filtering, and sample-rate reducing the sampled intermediate frequency using a digital filter for inherently generating a near zero complex intermediate frequency signal, and synchronously detecting the complex IF signal.
Abstract: A digital signal processing (DSP) radio receiver employs a conventional analog RF tuner to produce an analog intermediate frequency. The receiver performs DSP functions of digitally sampling the analog intermediate frequency at a sampling rate fs, concurrently mixing, filtering, and sample-rate reducing the sampled intermediate frequency using a digital filter for inherently generating a near-zero complex intermediate frequency signal, and synchronously detecting the complex IF signal. In a preferred embodiment, the invention is employed to reproduce AM stereo signals.

PatentDOI
TL;DR: A device for compressing a digital audio signal includes a device for allocating bits available for the transmission or storage of the signal, controlling means for the adaptive quantization of the signals in order to enable a major reduction in the bit rate while at the same time preserving the quality of the starting signal to the maximum extent.
Abstract: A device for compressing a digital audio signal, includes a device for allocating bits available for the transmission or storage of the signal, controlling means for the adaptive quantization of the signal, in order to enable a major reduction in the bit rate while at the same time preserving the quality of the starting signal to the maximum extent. The device includes means for allocating a specific number of bits for the expression of the coefficients of each frequency band of a transformed digital audio signal, as a function of a piece of auxiliary information corresponding to a description of the spectrum of the signal, said device being informed by means for the prior elimination of spectral components of said transformed signal as a function of a psychoauditive criterion.

Patent
08 May 1992
TL;DR: In this paper, a power amplifier controller for detecting saturation of the power amplifier (203) and correcting the automatic output control voltage (231) to avoid any further saturation is presented.
Abstract: A power amplifier controller for detecting saturation of the power amplifier (203) and correcting the automatic output control voltage (231) to avoid any further saturation. The controller detects the power of the RF output signal (211), generates a signal (229) correlated to the detected power, compares changes in that signal (229) to changes in the voltage of the AOC signal (231) in a comparator (217). The comparator (217) generates a signal (233) correlated to saturation of the power amplifier (203) for a DSP (223). The DSP checks the status of this signal (233). Upon detecting saturation, an algorithm contained within the DSP methodically reduces the voltage of the AOC signal (231) until there is a change in the power of the RF output signal (211).

Journal ArticleDOI
TL;DR: A novel forward-backward register allocation technique is proposed for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme.
Abstract: Systematic synthesis of digital signal processing (DSP) data format converter architectures using the minimum number of registers is addressed. Systematic lifetime analysis is used to calculate the minimum number of registers needed for the converter. A novel forward-backward register allocation technique is proposed for the synthesis of the converter; this allocation technique requires less area for the implementation of control circuits than a simpler forward-circulate allocation scheme. Furthermore, the forward-backward allocation scheme guarantees completion and sustains the interframe pipelining rate, whereas the forward-circulate scheme does not guarantee completion of the allocation. Examples of data format converters studied include matrix transposers, and a general (m, d/sub 1/) to (n, d/sub 2/)(w) converter, which processes m words and d/sub 1/ bits per word in one input cycle and outputs n words and d/sub 2/ bits per word in each output cycle. >

Journal Article
TL;DR: A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented, to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations.
Abstract: The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms.<>

Proceedings ArticleDOI
04 Aug 1992
TL;DR: The authors concentrate on the block diagram oriented software synthesis of digital signal processing systems for programmable processors, such as digital signal processors (DSP) and present the synthesis environment DESCARTES illustrating novel optimization strategies.
Abstract: For the design of complex digital signal processing systems, block diagram oriented simulation has become a widely accepted standard Current research is concerned with the coupling of heterogenous simulation engines and the transition from simulation to the implementation of digital signal processing systems Due to the difficulty in mastering complex design spaces high level hardware and software synthesis is becoming increasingly important The authors concentrate on the block diagram oriented software synthesis of digital signal processing systems for programmable processors, such as digital signal processors (DSP) They present the synthesis environment DESCARTES illustrating novel optimization strategies Furthermore they discuss goal directed software synthesis, by which code is interactively or automatically generated, which can be adapted to the application specific needs imposed by constraints on memory space, sampling rate or latency >

Patent
08 Dec 1992
TL;DR: A digital video signal converting apparatus for converting a first digital signal having a first resolution to a second digital signal with a second resolution higher than the first resolution, comprises; block segmentation circuit, memory having a mapping table stored therein and having address terminals to which the first digital video signals in a block format are supplied, and output terminals from which the second digital signals in block format is output, and block separation circuit, wherein the mapping table in the memory is generated by training utilizing a plurality of images as mentioned in this paper.
Abstract: A digital video signal converting apparatus for converting a first digital video signal having a first resolution to a second digital video signal having a second resolution higher than the first resolution, comprises; block segmentation circuit for converting the first digital video signal into a block format, memory having a mapping table stored therein and having address terminals to which the first digital video signal in a block format is supplied and output terminals from which the second digital video signal in block format is output, and block separation circuit for converting the second digital video signal in a block format into a digital video signal in a raster scan order, wherein the mapping table in the memory is generated by training utilizing a plurality of images the training step being performed by generating first and second digital video signal corresponding to each of the plurality of images, converting each of the first and second digital video signals into a block format, and selecting the first digital video signal in a block format is an address signal for the mapping table and inputting the second digital video signal in a block format to a memory area corresponding to the address, and generating data of the mapping table from the signal stored in the memory area.

Journal ArticleDOI
M. Runde, T. Aurud, L.E. Lundgaard, G.E. Ottesen1, K. Faugstad 
TL;DR: In this paper, a noninvasive technique for assessing the condition of circuit breakers by considering the acoustic signals generated during nonenergized switching is described, which can be detected as changes in this acoustic signature.
Abstract: A noninvasive technique for assessing the condition of circuit breakers by considering the acoustic signals generated during nonenergized switching is described. Mechanical malfunction, wear, and other types of abnormal behavior can be detected as changes in this acoustic signature. Digital signal processing techniques known from speech recognition were successfully applied to extract, compare, and present the information from the breaker signatures. A fault in the release mechanism which developed over time and eventually rendered one pole of a circuit-breaker inoperative was detected in an early stage, demonstrating the efficiency of this diagnostic technique. >

Patent
30 Sep 1992
TL;DR: In this article, a band compression signal processor designed to convert video signals or the like into digital signals and to perform band compression by effecting both intra-frame encoding and interframe encoding is presented.
Abstract: A band compression signal processor designed to convert video signals or the like into digital signals and to perform band compression by effecting both intra-frame encoding and inter-frame encoding. The signal output by the processor is supplied to a recording/reproducing apparatus. In the apparatus, the signal is recorded on a magnetic tape and reproduced therefrom by helical scanning method. The signal intra-frame-encoded is arranged within such a region as to be read out in fast reproduction mode.

Patent
Fetchi Chen1, Jose A. Eduartez1, Charles R. Knox, Ronald J. Lisle, Raymond W. Weeks 
13 Oct 1992
TL;DR: In this article, a centralized digital signal processor resource manager acquires through software techniques, configuration and related data for multimedia hardware devices from BIOS device drivers interposed to functionally insulate the resource manager from hardware device specific information.
Abstract: A centralized digital signal processor resource manager acquires through software techniques, configuration and related data for multimedia hardware devices from BIOS device drivers interposed to functionally insulate the resource manager from hardware device specific information. The resource manager manages hardware devices in a multiple DSP environment using a unique software based hardware device identification scheme to identify and manage the location and availability of each hardware device.


Patent
17 Aug 1992
TL;DR: In this paper, a low-bit-rate, low-cost, all-digital preambleless demodulator for maritime and mobile data communications operates under severe high noise conditions, fast Doppler frequency shifts, large frequency offsets, and multipath fading.
Abstract: A low-bit-rate, low-cost, all-digital preambleless demodulator for maritime and mobile data communications operates under severe high noise conditions, fast Doppler frequency shifts, large frequency offsets, and multipath fading. Sophisticated algorithms, including an FFT-based burst acquisition system, a cycle-slip resistant carrier phase tracker, an innovative Doppler tracker, and a fast acquisition symbol synchronizer, provide reliable burst reception. The compact DSP-based demodulator includes an input buffer receiving a complex sampled baseband input signal and providing a baseband output to a coarse frequency estimator fast Fourier transform (FFT) or discrete Fourier transform (DFT) module which produces a first estimation of the carrier frequency. A fine frequency estimator FFT or DFT module receives the first estimation and provides a second estimation of the carrier frequency. An extra coarse frequency estimator FFT or DFT module may be provided between the buffer and the coarse frequency estimator.