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Showing papers on "Digital signal processing published in 1997"


Book
01 May 1997
TL;DR: A number of new topics have been added to the second edition of "Digital Signal Processing: A Computer-Based Approach", based on user feedback, and the author has taken great care to organize the chapters more logically by reordering the sections within chapters.
Abstract: From the Publisher: "Digital Signal Processing: A Computer-Based Approach" is intended for a two-semester course on digital signal processing for seniors or first-year graduate students. Based on user feedback,a number of new topics have been added to the second edition,while some excess topics from the first edition have been removed. The author has taken great care to organize the chapters more logically by reordering the sections within chapters. More worked-out examples have also been included. The book contains more than 500 problems and 150 MATLAB exercises. New topics in the second edition include: finite-dimensional discrete-time systems,correlation of signals,inverse systems,system identification,matched filter,design of analog and IIR digital highpass,bandpass and bandstop filters,more on FIR filters,spectral analysis of random signals and sparse antenna array design.

1,470 citations


Book
01 Dec 1997
TL;DR: This volume, Wireless, Networking, Radar, Sensor Array Processing, and Nonlinear Signal Processing, provides complete coverage of the foundations of signal processing related to wireless, radar, spacetime coding, and mobile communications, together with associated applications to networking, storage, and communications.
Abstract: From the Publisher: The field of digital signal processing (DSP) has spurreddevelopments from basic theory of discrete-time signals and processing tools to diverse applications in telecommunications, speech and acoustics, radar, and video. This volume provides an accessible reference, offering theoretical and practical information to the audience of DSP users. This immense compilation outlines both introductory and specialized aspects of information-bearing signals in digital form, creating a resource relevant to the expanding needs of the engineering community. It also explores the use of computers and special-purpose digital hardware in extracting information or transforming signals in advantageous ways. Impacted areas presented include: Telecommunications Computer engineering Acoustics Seismic data analysis DSP software and hardware Image and video processing Remote sensing Multimedia applications Medical technology Radar and sonar applications This authoritative collaboration, written by the foremost researchers and practitioners in their fields, comprehensively presents the range of DSP: from theory to application, from algorithms to hardware.

427 citations



Journal ArticleDOI
TL;DR: A real-time system that uses wavelet transforms to overcome the limitations of other methods of detecting QRS and the onsets and offsets of P- and T-waves is described.
Abstract: The rapid and objective measurement of timing intervals of the electrocardiogram (ECG) by automated systems is superior to the subjective assessment of ECG morphology. The timing interval measurements are usually made from the onset to the termination of any component of the EGG, after accurate detection of the QRS complex. This article describes a real-time system that uses wavelet transforms to overcome the limitations of other methods of detecting QRS and the onsets and offsets of P- and T-waves. Wavelet transformation is briefly discussed, and detection methods and hardware and software aspects of the system are presented, as well as experimental results.

361 citations


Journal ArticleDOI
TL;DR: In this article, a general noise-shaping DAC architecture along with two special-case configurations that achieve first and second-order noise shaping, respectively, are presented, and a rigorous explanation of the apparent paradox of how DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noiseshaping algorithm.
Abstract: Recently, various multibit noise-shaping digital-to-analog converters (DACs) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DACs have the potential to significantly increase the present precision limits of /spl Delta//spl Sigma/ data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise-the errors introduced by the analog circuitry-are not known to the noise-shaping algorithm.

321 citations


Patent
06 May 1997
TL;DR: In this article, the authors proposed a handshake protocol and receiver algorithm for CAP-based MDSL modems, which allows reliable modem synchronization over severely amplitude distorted channels and makes use of a short length sequence to train a synchronizing equalizer at the receiver.
Abstract: A modem operating selectively in the voice frequency and higher frequency bands which supports multiple line codes. A DSP is used to implement different existing ADSL line codes on the same hardware platform. The modem negotiates in real time for a desired line transmission rate to accommodate line condition and service cost requirements which may be implemented at the beginning of each communication session by exchange of tones between modems. A four step MDSL modem initialization process provides line code and rate compatibility. The handshake protocol and receiver algorithm for CAP based MDSL modems allows reliable modem synchronization over severely amplitude distorted channels and makes use of a short length sequence to train a synchronizing equalizer at the receiver. The algorithm and corresponding training sequence to train the transmitter filter are provided. After training to this sequence, a matched filter or correlator detects the inverted sync sequence. Detection of the inverted sequence signals commencement of normal reference training of the demodulation equalizers. An internal state machine in an MDSL modem records and monitors line status and notifies state change to other MDSL and host processor. The protocol for exchanging line connection management messages is a simplified LCP for MDSL. In a DMT system, a transmitter filter reduces the length of effective channel impulse response. Iimplementation of the filter combines time domain convolution and frequency domain multiplication to reduce needed computation power. The filter coefficients update may occur through a feedback channel.

292 citations


Journal ArticleDOI
TL;DR: In this article, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements, and a scheduling technique based on the new instruction level power model is proposed.
Abstract: Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged.

284 citations


Proceedings ArticleDOI
05 Oct 1997
TL;DR: In this paper, a new simple control strategy for AC input current of voltage-type PWM rectifiers which can eliminate the steady-state control error completely is proposed, which requires neither the instantaneous value of the supply voltage nor any accurate circuit parameters on the AC side of the rectifier.
Abstract: In this paper, a new simple control strategy for AC input current of voltage-type pulsewidth modulation (PWM) rectifiers which can eliminate the steady-state control error completely is proposed. This control method requires neither the instantaneous value of the supply voltage nor any accurate circuit parameters on the AC side of the rectifier. Thus, a robust operation against the variation of the circuit parameters can be achieved. In the proposed control system, a digital resonant element implemented by a digital signal processor (DSP) is introduced as a feedback controller. The digital resonant element exhibits a function similar to an integrator for the fundamental frequency components. Thus, it can eliminate the steady-state control error of the input current completely, The principle of the proposed control method is discussed, and its effectiveness is shown theoretically. The detailed method of the implementation of the lossless digital resonant element is explained. The effects of the harmonics in the supply voltage on the AC input current waveform are clarified. To confirm the effectiveness of the proposed control method, some experimental results from two laboratory test systems are shown.

277 citations


Patent
18 Feb 1997
TL;DR: In this article, a system for digital image capture and transmission includes an image fulfillment server, having a transceiver for sending and receiving channel assessment signals and receiving a digital image file and a memory for storing the received digital image files.
Abstract: A system method for digital image capture and transmission includes an image fulfillment server, having a transceiver for sending and receiving channel assessment signals and receiving a digital image file and a memory for storing the received digital image file. The system also includes a digital camera having an electronic image sensor for sensing an image and producing a digital image; a short term memory for storing digital images produced by the image sensor in digital image files; a transceiver for communicating with and transmitting the digital image files to the image fulfillment server; a signal strength detector for monitoring the registration signal from the fulfillment server and producing a transmit enable signal; a long term memory for storing the digital image files; the transmit enable signal for disabling transmission of the digital image data when the channel assessment signal indicates that successful transmission of the digital image data is not possible; and a timer for transferring the digital image file from the short term memory to the long term memory after a predetermined period of time.

254 citations


Journal ArticleDOI
TL;DR: Digital signal processing technology provides the speed and flexibility needed to satisfy the requirements of real-time EEG analysis in real time, and supports evaluation of alternative analysis and control algorithms, and thereby facilitates further BCI development.
Abstract: We are developing an electroencephalographic (EEG)-based brain-computer interface (BCI) system that could provide an alternative communication channel for those who are totally paralyzed or have other severe motor impairments. The essential features of this system are as follows: (1) EEG analysis in real time, (2) real-time conversion of that analysis into device control, and (3) appropriate adaptation to the EEG of each user. Digital signal processing technology provides the speed and flexibility needed to satisfy these requirements. It also supports evaluation of alternative analysis and control algorithms, and thereby facilitates further BCI development.

181 citations


Journal ArticleDOI
TL;DR: In this paper, a novel technique for space-vector modulation (SVM) inverters in the overmodulation range is presented, which is suitable for a very simple digital implementation.
Abstract: A novel technique for space-vector modulation (SVM) inverters in the overmodulation range is presented. A unique algorithm manages the transition from the onset of overmodulation to six-step operation. The technique is suitable for a very simple digital implementation. Experimental results, obtained by a digital signal processor (DSP) board, are also included in this paper.

Patent
28 Mar 1997
TL;DR: In this article, the authors proposed a method for the joint detection of multiple coded digital signals that share the same transmission medium in a manner that causes mutual interference, consisting of two steps that are applied to preliminary estimates of each digital signal, one or more times.
Abstract: A method for the joint detection of multiple coded digital signals that share the same transmission medium in a manner that causes mutual interference. The method is comprised of two steps that are applied to preliminary estimates of each digital signal, one or more times. The first step is to obtain reliability estimates for each data element of each digital signal by combining the preliminary estimates, a statistical model for the interference, and any a priori information regarding the data elements. The second step is to revise these reliability estimates for each digital signal based on the forward error correction code used for that digital signal. When the steps are repeated, the revised reliability estimates from the second step are used as a priori information for the first step.

Patent
22 May 1997
TL;DR: In this article, an integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office.
Abstract: An integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office. The line card contains analog line circuitry such as a ring generator, off-hook detector, D.C. current feed, and a single analog-digital (A/D) converter. The phone line carries a composite signal of both the high-frequency ADSL data and the low-frequency voice or plain-old-telephone-service (POTS) signal. Instead of using an analog frequency-splitter with bulky, expensive inductor coils, a digital splitter is used. A digital-signal processor (DSP) can be used to perform the digital splitting of ADSL and POTS. The waveforms from the analog phone line are first converted to digital values by the A/D converter, and then a digital splitter separates the low-frequency POTS from the high-frequency ADSL. The ADSL data is formatted by the DSP for a data pathway to the Internet, while the POTS data is converted by the DSP to A-Law or C-Law for transmission over the telephone network's PCM highway. The DSP can perform all decoding, encoding, compression, and formatting needed by both ADSL and POTS. The quality of the phone line is improved by having a single termination point at the central office, rather than separate termination points for POTS and ADSL data from the phone line.

Journal ArticleDOI
TL;DR: In this article, an active power filter based on a digital signal processing (DSP) controller with enhanced current control performance is presented, where a novel predictive current control method is introduced to compensate the phase error of harmonic components caused by discrete sampling and finite nonnegligible execution time delay.
Abstract: This paper presents an active power filter based on a digital signal processing (DSP) controller with enhanced current control performance. A novel predictive current control method is introduced to compensate the phase error of harmonic components caused by discrete sampling and finite nonnegligible execution time delay. The concept of average current control is also introduced that is adequate for digital current control. With a close coordination between the reference current prediction, PWM pattern generation, and control timing, a high performance control is achieved. Experimental results show that the developed system gives satisfactory performance in harmonic and reactive power compensation.

Patent
01 Aug 1997
TL;DR: In this paper, a dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed, and a precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal.
Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Journal ArticleDOI
TL;DR: In this paper, an on-chip infrared remote control receiver is used to load a program into the digital signal processor (DSP), which consumes 2 mW from a single cell battery and operates with supply voltages down to 0.9 V.
Abstract: This paper presents a digital signal processing IC, including AD/DA converters, for one-chip hearing instruments. An on-chip infrared remote control receiver is used to load a program Into the digital signal processor (DSP). The complete IC consumes 2 mW from a single cell battery and operates with supply voltages down to 0.9 V. The oversampling A/D and D/A converters show a dynamic range of 77 and 93 dBA, respectively. Only a few external capacitors are needed. The chip area is 35 mm/sup 2/ in a low-threshold 0.8-/spl mu/m CMOS process.

Patent
11 Jun 1997
TL;DR: A portable acoustic signal (speech signal) preprocessing (SSP) device for accessing an automatic speech/speaker recognition (ASSR) server comprises a microphone for converting sound including speech, silence and background noise signals to analog signals; an analog signals to digital converter for converting the analog signal to digital signals; a digital signal processor (DSP) for generating feature vector data representing the digitized speech and silence/background noise, and for generating channel characterization signals; and an acoustic coupler for converting feature vector signals and the characterization signals to acoustic signals and coupling the acoustic signals
Abstract: A portable acoustic signal (speech signal) preprocessing (SSP) device for accessing an automatic speech/speaker recognition (ASSR) server comprises a microphone for converting sound including speech, silence and background noise signals to analog signals; an analog signals to digital converter for converting the analog signals to digital signals; a digital signal processor (DSP) for generating feature vector data representing the digitized speech and silence/background noise, and for generating channel characterization signals; and an acoustic coupler for converting the feature vector data and the characterization signals to acoustic signals and coupling the acoustic signals to a communication channel to access the ASSR server to perform speech and speaker recognition at a remote location. The SSP device may also be configured to compress and encrypt data transmitted to the ASSR server via the DSP and encryption keys stored in a memory. The ASSR server receives the preprocessed acoustic signals to perform speech/speaker recognition by setting references, selecting appropriate decoding models and algorithms to decode the acoustic signals by modeling the channel transfer function from the channel characterization signals and processing the silence/background noise data to reduce word error rate for speech recognition and to perform accurate speaker recognition. A client/server system having the portable SSP device and the ASSR server can be used to remotely activate, reset, or change personal identification numbers (PINs) or user passwords for smartcards, magnetic cards, or electronic money cards.

Patent
19 Dec 1997
TL;DR: In this paper, a multi-mode, multi-band and multi-user radio system architecture is presented. But the architecture is not suitable for the use of a single-input single-output (SIMO) channel.
Abstract: A multi-mode, multi-band, multi-user radio system architecture includes four channels of exciter circuits and receiver circuits coupled to a digital signal processing array. Each of the exciter and receiver circuits includes three separate signal paths for three separate frequency ranges of analog signals. Each path includes an analog-to-digital converter or a digital-to-analog converter for converting both modulated analog signals to modulated digital signals and modulated digital signals to modulated analog signals. The digital signal processing array performs modulation and demodulation functions for the radio system.

Patent
Johan Lodenius1
22 May 1997
TL;DR: In this article, a single chip CMOS technology architecture is used to implement all or various combinations of baseband radio transmission, baseband interfaces and filtering, source coding, source interfaces, control and supervision, power and clock management, keyboard and display drivers, memory management and code compaction, digital signal processing ( DSP ) and DSP memory and radio interface functions.
Abstract: According to the present invention, a single chip semiconductor devices is provided. In one version of the invention, a single chip CMOS technology architecture is used to implement all or various combinations of baseband radio transmission, baseband interfaces and filtering, source coding, source interfaces and filtering, control and supervision, power and clock management, keyboard and display drivers, memory management and code compaction, digital signal processing ( DSP ) and DSP memory and radio interface functions.

Patent
James C. Kolanek1
25 Nov 1997
TL;DR: In this article, a digital direction finding receiver with N frequency channels (50a, 50e) spanning a frequency band of the receiver and capable of receiving signals simultaneously from a plurality of antennas (30a, 30e) spaced from one another, one of the antennas including a reference location antenna.
Abstract: The invention is embodied in a digital direction finding receiver having N frequency channels (50a, 50e) spanning a frequency band of the receiver and capable of receiving signals simultaneously from a plurality of antennas (30a, 30e) spaced from one another, one of the antennas including a reference location antenna. The receiver of the invention includes a plurality of analog-to-digital converters (32a, 32e) having their analog inputs connected to respective ones of the antennas, a reference source (58) capable of outputting a reference digital signal containing at least a local frequency component within a selected one of the N frequency channels, a plurality of digital down converter modules (50a, 50e), each one of the digital down converter modules having a reference input connected to the reference source and a signal input connected to the digital output of a respective one of the analog-to-digital converters, each the digital down converter modules including a multiplier (56a, 56e) for producing at an output of the digital down converter a product of the reference signal and the signal from the respective one of the antennas, and a digital phase detector (35) having plural phase detector signals inputs connected to the outputs of remaining ones of the digital down converters, the phase detector detecting phase angles of the signals on each of the phase detector signal inputs relative to a corresponding signal received at the reference antenna.

01 Jan 1997
TL;DR: The FPGA approach to digital filter implementation includes higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches.
Abstract: Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application-specific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs). The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. Our examples illustrate that the FPGA approach is both flexible and provides performance comparable or superior to traditional approaches.

PatentDOI
TL;DR: An audio teleconferencing apparatus and method provide an audio sound field among a plurality of teleconferencees creating a sense of a virtual conference table having a spatial location for each conferencee at the virtual table.
Abstract: An audio teleconferencing apparatus and method provide an audio sound field among a plurality of teleconferencees creating a sense of a virtual conference table having a spatial location for each conferencee at the virtual table. Each conferencee has a speakerphone including a programmable Digital Signal Processor (DSP) for receiving a conference audio signal. In one form, the speakerphones are coupled to a conference bridge through individual ports, the bridge linking together all conferencees for purposes of the multiparty teleconference and transmitting port identifying signals denoting at discrete instants of time which remote port has a currently speaking conferences. The port identity signals are transmitted in-band or out-of-band to the speakerphones in conjunction with the conference audio signal. Each speakerphone uses the programmed DSP and the port identity signal/audio signals to cause sound reproduced at the speakerphone to appear to emanate from positions around the virtual conference table according to the port identity signals. In another form, a conference speakerphone exchanges its ID with other conference phones on the call and creates an "outgoing image" of participants at a speakerphone. Using the Id information, each DSP maps a virtual conference table for the conferencees and the relative spatial positions of the speakers within a group.

Patent
TL;DR: In this paper, a digital signal processing hearing aid is disclosed having a plurality of signal processing means for processing input digital signals, and a selector switch manipulable by a user for choosing which of the processing means to utilize.
Abstract: A digital signal processing hearing aid is disclosed having a plurality of digital signal processing means for processing input digital signals, and a selector switch manipulable by a user for choosing which of the processing means to utilize. Each of the digital signal processing means is designed to provide optimal results in a particular listening environment. Since the user is allowed to choose which of the plurality of processing means to invoke, and since each processing means is specifically designed to operate in a particular listening environment, the hearing aid is capable of providing excellent results in a plurality of listening environments.

Patent
26 Nov 1997
TL;DR: In this paper, the processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the devices.
Abstract: The processing speed of a digital signal processor or system processor is controlled in accordance with the functions required in a task to be performed by the device, with these functions being compared to a table of maximum processing speeds at which various functions can be performed reliably by the device. This method is applied to a number of digital signal processors on a communications adapter, with a core kernel of each of these digital signal processors being driven at a processing speed controlled in this way, while peripheral functions of all these digital signal processors are performed according to a clock signal synchronized with data being received from a network transmission line.

Patent
28 Feb 1997
TL;DR: In this article, the authors proposed a scheme to detect the presence of IMD interference in a CDMA cellular or broadband PCS mobile phone receiver by spectral estimation, which is performed by collecting a series of data samples from the received signal and, using a digital signal processor (DSP), computing a Discrete Fourier Transform (DFT) to generate frequency domain data, passing the data through a filter bank, then using a decision algorithm to determine whether or not there is sufficient IMD present in the receiving signal to bypass the LNA.
Abstract: In the front end of a CDMA cellular or broadband PCS mobile phone receiver, a switched bypass connection is provided to bypass the low noise amplifier, sending the received signal through an amplifier bypass connection. The amplifier bypass connection may include an attenuator. The switched bypass is activated by a control signal generated by a digital signal processor. The digital signal processor analyzes the received signal to detect and determine the relative contribution of the IMD interference to the total received signal power and, when the IMD interference exceeds a predetermined level, sends a control signal to bypass the low noise amplifier. Identification of the presence of IMD interference is by spectral estimation to discern when the mobile phone is in the presence of large near-band signals from an AMPS or other narrow-band base station which causes in-band IMD. In a preferred embodiment, the spectral estimation is performed by collecting a series of data samples from the received signal and, using a digital signal processor (DSP), computing a Discrete Fourier Transform (DFT) to generate frequency domain data, passing the data through a filter bank, then using a decision algorithm to determine whether or not there is sufficient IMD present in the received signal to bypass the LNA. If the IMD level is high enough to warrant bypass of the LNA, the DSP will provide a signal to an automatic gain control (AGC) block for controlling a variable gain amplifier (VGA) to compensate for gain loss due to bypass of the LNA.

Journal ArticleDOI
TL;DR: In this paper, the authors advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications, based on the runtime characteristics of signal processing applications.
Abstract: Power consumption analyzes of embedded processors indicate that a significant amount of power is consumed in accessing memory and in the control path. Based on this, and on the runtime characteristics of signal processing applications, we advocate the use of instruction buffering as a power-saving technique for processors for signal processing and multimedia applications. Two approaches, a decoded instruction buffer (DIB) and a decoded instruction cache, are considered. Performance improvements in representative applications in speech processing such as, the vector sum excited linear prediction (VSELP), linear prediction coding coefficient computation (LPC), and two-dimensional 2-D 8/spl times/8 DCT which is used in image compression, are provided. The reduction in power obtained is between between 25 and 30%.

Proceedings Article
01 Jan 1997
TL;DR: In this paper, a review of algorithms for perceptually transparent coding of high-fidelity (CD-quality) digital audio signals is presented, including algorithms which manipulate transform components and subband signal decompositions.
Abstract: Considerable research has been devoted to the development of algorithms for perceptually transparent coding of high-fidelity (CD-quality) digital audio. As a result, many algorithms have been proposed and several have now become international and/or commercial product standards. This paper reviews algorithms for perceptually transparent coding of CD-quality digital audio, including both research and standardization activities. First, psychoacoustic principles are described with the MPEG psychoacoustic signal analysis model 1 discussed in some detail. Then, we review methodologies which achieve perceptually transparent coding of FM- and CD-quality audio signals, including algorithms which manipulate transform components and subband signal decompositions. The discussion concentrates on architectures and applications of those techniques which utilize psychoacoustic models to exploit efficiently masking characteristics of the human receiver. Several algorithms which have become international and/or commercial standards are also presented, including the ISO/MPEG family and the Dolby AC-3 algorithms. The paper concludes with a brief discussion of future research directions.

Patent
30 Jul 1997
TL;DR: In this article, a copyright information embedding system for digital audio signals without deterioration of analog audio signals is presented, which includes an A/D converter, a modulator, a level detector, and a copyright data embedding circuit.
Abstract: A copyright information embedding system is provided which is designed to embed information for copyright protection into digital audio signals without deterioration of analog audio signals reproduced. The copyright information embedding system includes an A/D converter, a modulator, a level detector, and a copyright data embedding circuit. The A/D converter converts an analog audio signal into a digital signal. The modulator modulates a copyright data signal for the digital signal using spectrum spread. The level detector detects a variation in level of the digital signal. The copyright data embedding circuit divides the copyright data signal into several codes and embeds them into the digital signal each time the variation in level of the digital signal shows a preselected variation such as a rapid rise or drop.

Journal ArticleDOI
R. Miura, T. Tanaka1, I. Chiba2, A. Horie, Y. Karasawa 
TL;DR: In this paper, the authors describe a digital beamforming (DBF) multibeam antenna that incorporates a compact digital signal processor (DSP) engine and the results of using it in a beamforming experiment receiving a satellite signal in a land-mobile environment.
Abstract: This paper describes a digital beamforming (DBF) multibeam antenna that incorporates a compact digital signal processor (DSP) engine, and the results of using it in a beamforming experiment receiving a satellite signal in a land-mobile environment. A considerable reduction in the scale of the DSP engine has been achieved by using field programmable gate arrays (FPGAs). To capture a satellite signal arriving from an unknown direction, a two-dimensional (2-D) spatial FFT signal processing provides orthogonal multibeam patterns on the broad side of a planar array antenna. The experimental results demonstrated the features of coarse acquisition and tracking of a signal arrival by selecting the strongest of the beams without assistance from direction finding sensors or microwave phase shifters. The DBF multibeam antenna will provide high-quality communications and increase traffic capacity if it is applied to high-gain mobile antennas or multispot-beam base station antennas in cellular or satellite mobile communications.

Patent
26 Sep 1997
TL;DR: In this article, a dynamic volume control system in an audio processor uses gain and delay signals from a digital signal processor to dynamically control the user-selected volume of the audio processor.
Abstract: A dynamic volume control system in an audio processor uses gain and delay signals from a digital signal processor to dynamically control the user-selected volume of the audio processor. The digital signal processor executes audio signal processing operations that affect the gain applied to the audio signal so that the signal gain inherent in the signal processing path is known. The digital signal processor transfers the known gain and a predicted group delay signal to the dynamic volume control system to dynamically adjust the user-selected volume of the system. The digital signal processor is integrated with a digital-to-analog converter (DAC) in a dynamic volume control system that exploits the known gain and group delay to perform DAC volume control.