Showing papers on "Digital signal processing published in 2001"

Recurrent Neural Networks for Prediction: Learning Algorithms,Architectures and Stability

Abstract: From the Publisher: From mobile communications to robotics to space technology to medical instrumentation, new technologies are demanding increasingly complex methods of digital signal processing (DSP). This book shows researchers how recurrent neural networks can be implemented to expand the range of traditional signal processing techniques. Featuring original research on stability in neural networks, the book combines rigorous mathematical analysis with application examples. Experimental evidence as well as an overview of existing approaches are also included. Market: Engineers working in signal processing, neural networks, communications, nonlinear control, and time series analysis.

Digital Signal Processing with Field Programmable Gate Arrays

Abstract: Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing as novel FPGA families are replacing ASICs and PDSPs for front-end digital signal processing algorithms So the efficient implementation of these algorithms is critical and is the main goal of this book It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems A case study in the first chapter is the basis for more than 40 design examples throughout The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters Each chapter contains exercises The VERILOG source code and a glossary are given in the appendices, while the accompanying CD-ROM contains the examples in VHDL and Verilog code as well as the newest Altera "Quartus II web edition" software This edition has a new chapter on microprocessors, new sections on special functions using MAC calls, intellectual property core design and arbitrary sampling rate converters, and over 100 new exercises

Advanced methods for I/Q imbalance compensation in communication receivers

Abstract: I/Q signal processing is widely utilized in today's communication receivers However, all I/Q processing receiver structures, such as the low-IF receiver, face a common problem of matching the amplitudes and phases of the I and Q branches In practice, imbalances are unavoidable in the analog front-end, which results in finite and usually insufficient rejection of the image frequency band This causes the image signal to appear as interference on top of the desired signal We carry out general signal analysis of an imbalanced I/Q processing receiver and propose novel methods for I/Q imbalance compensation using baseband digital signal processing A simple structure for compensation is derived, based on a traditional adaptive interference canceller Improved image rejection can also be obtained by using more advanced blind source separation techniques Theoretical analysis of the performance of the proposed imbalance compensation structures is presented In addition, some simulation results are provided in order to further evaluate the performance of the proposed methods The results indicate that the I/Q imbalance can be effectively compensated during the normal operation of the receiver even in the rapidly changing case, as long as a linear system model for the imbalance is valid

Reconfigurable Computing for Digital Signal Processing: A Survey

Abstract: Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance. This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.

Soft digital signal processing

Abstract: In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delay imbalance" are employed. A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60-81% reduction in energy dissipation for filter bandwidths up to 0.5 /spl pi/ (where 2 /spl pi/ corresponds to the sampling frequency f/sub s/) over that achieved via conventional architecture and voltage scaling, with a maximum of 0.5-dB degradation in the output signal-to-noise ratio (SNR/sub o/). It is also shown that the proposed algorithmic noise-tolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10/sup -3/ due to deep submicron (DSM) noise.

Real-time digital signal processing

Abstract: Preface. Chapter 1. Introduction to Real-Time Digital Signal Processing. Chapter 2. Introduction to TMS320C55x Digital Signal Processor. Chapter 3. DSP Fundamentals and Implementation Considerations. Chapter 4. Design and Implementation of FIR Filters. Chapter 5. Design and Implementation of IIR Filters. Chapter 6. Frequency Analysis and Fast Fourier Transform. Chapter 7. Adaptive Filtering. Chapter 8. Digital Signal Generators. Chapter 9. Dual-Tone Multi-Frequency Detection. Chapter 10. Adaptive Echo Cancellation. Chapter 11. Speech Coding Techniques. Chapter 12. Speech Enhancement Techniques. Chapter 13. Audio Signal Processing. Chapter 14. Channel Coding Techniques. Chapter 15. Introduction to Digital Image Processing. Appendix A: Some Useful Formulas and Definitions. A.1 Trigonometric Identities. A.2 Geometric Series. A.3 Complex Variables. A.4 Units of Power. References. Appendix B: Software Organization and List of Experiments. Index.

Combined word-length optimization and high-level synthesis of digital signal processing systems

Abstract: Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software.

Methods and apparatus for image capture and decoding in a centralized processing unit

Abstract: An improved method and device for capturing image data benefits from having a single central processor execute the operating system, and the image capture, decode and processing programs. A method for capturing of image data comprises transmitting image data from an imager, assembling the image data, assigning a memory address to the assembled image data and transferring the assembled image data into system memory. This method is capable of central processing whereby the capturing of image data is executed via the main processor without having to invoke a dedicated processor or incorporate external components, such as additional PCBs, external digital signal processing or external data storage. Additionally, an imaging device comprises an image builder module that receives image data from the imager bus and assembles the data, and a transfer controller that initiates the image builder module and controls the transfer of image data into and out of memory.

Compensation of frequency-selective I/Q imbalances in wideband receivers: models and algorithms

Abstract: To achieve satisfactory performance in analog I/Q (inphase/quadrature) processing-based wireless receivers, the matching of amplitudes and phases of the I and Q branches becomes vital. In practice, there is always some imbalance and the image attenuation produced by the analog processing remains finite. Especially in wideband receivers, where the existence of strong image band signals makes the attenuation requirements extremely stringent, analog processing is incapable of providing adequate image rejection. We derive a general frequency-dependent signal model for an imbalanced analog front-end and present two alternative methods utilizing digital processing to enhance the analog front-end image rejection. Based on the obtained results, the proposed methods provide adequate image signal rejection with very few assumptions, even in the difficult cases of frequency-selective and/or time-varying imbalances.

Gain/phase imbalance-minimization techniques for LINC transmitters

Abstract: Two simple calibration schemes for the correction of the path imbalance in a linear amplification with nonlinear components (LINC) transmitter have been demonstrated. In the foreground algorithm, a baseband digital signal processor (DSP) evaluates the gain and phase imbalance with a set of calibration signals, while in the background algorithm, the imbalance is characterized by exchanging the two LINC vector components. In both cases, the compensation of the path imbalance is accomplished within the DSP by introducing a predistortion term. A prototype LINC system has been tested for CDMA IS-95 baseband input, and -38 and -35-dBc adjacent channel interference were achieved for the foreground and background schemes, respectively. The quadrature errors of the in-phase/quadrature modulators set a limit on the overall performance of both algorithms.

Novel sampling algorithm for DSP controlled 2 kW PFC converter

Abstract: This paper proposes a novel sampling algorithm for digital signal processing (DSP) controlled 2 kW power factor correction (PFCs) converters, which can improve switching noise immunity greatly in average-current-control power supplies. Based on the newly developed DSP chip TMS320F240. a 2 kW PFC stage is implemented. The novel sampling algorithm shows great advantages when the converter operates at a frequency above 30 kHz.

Digital generation of RF signals for wireless communications with band-pass delta-sigma modulation

Abstract: This paper demonstrates a high speed digital technique to produce binary (digital) signals that encode representative RF signals (with time varying envelope) as needed for wireless communications. Specifically, it shows that IS-95 format CDMA signals can be generated with a single bit digital data stream at 3.6 Gb/S. The technique uses band-pass delta-sigma modulation so that the quantization noise is shaped out of the frequency band of interest. This approach points the way to single-chip, DSP-based transmitters, used in conjunction with switching mode power amplifiers and simple analog filters, to implement all the functions of a wireless transmitter.

Fundamentals of Digital Signal Processing

Abstract: 1. Crash Course in Digital Signal Processing. 2. Analog-to-Digital and Digital-to-Analog Conversion. 3. Digital Signals. 4. Difference Equations and Filtering. 5. Convolution and Filtering. 6. z Transforms. 7. Fourier Transforms and Filter Shape. 8. Digital Signal Spectra. 9. Finite Impulse Response Filters. 10. Infinite Impulse Response Filters. 11. DFT and FFT Processing. 12. Hardware for DSPs. 13. Programming DSPs. 14. Signal Processing. 15. Image Processing. 16. Wavelets. References. Appendices. Index.

Synergistic design of DSP and power amplifiers for wireless communications

Abstract: Co-design of digital signal-processing (DSP) algorithms and power-amplifier characteristics can lead to improved efficiency and linearity through a variety of strategies including: predistortion, DSP control over bias conditions, particularly the power supply voltage, and DSP generation of digital input signals for switching amplifiers. This paper discusses several amplifier architectures that exemplify these approaches, including: bias-controlled amplifiers, linear amplification with nonlinear component amplifiers, and class-S amplifiers. We envision for the future a generation of "smart power amplifiers," in which DSP optimization of amplifier parameters is carried out for changing environments.

Apparatus and method for perceiving physical and emotional state

Abstract: An apparatus and method for perceiving a physical and emotional state, which allows easy attachment to and detachment from a human body, and through which a bio-signal is simply detected, are provided. The apparatus includes a bio-signal detection part attached to a predetermined portion of a body for performing analog signal processing on at least one bio-signal detected from the body and outputting the processed bio-signal, and a bio-signal recognizing part for performing digital signal processing on the processed bio-signal received from the bio-signal detection part, perceiving the physical and emotional state from the result of the digital signal processing, and representing the physical and emotional state. Accordingly, the apparatus can be conveniently attached to a predetermined portion of a user's body, a bio-signal transmitted wirelessly or through a wire can be easily detected, a physical and emotional state which is perceived based on the detected bio-signal can be reported to the user, and a rapidly changing emotional state or an emotional state which remains for a long time can be perceived in real time.

Secure scalable video streaming for wireless networks

Abstract: The conference proceedings are published in six volumes. Volume I deals with speech processing. Volume II deals with: speech processing; industry technology track; design and implementation of signal processing systems; neural networks for signal processing. Volume III deals with: image and multidimensional signal processing; multimedia signal processing. Volume IV deals with signal processing for communications. Volume V deals with:signal processing education; sensor array and multichannel signal processing; audio and electroacoustics. Volume VI deals with signal processing theory and methods

Sonic/ultrasonic authentication device

Abstract: A method for verifying and identifying users, and for verifying users' identity, by means of an authentication device capable of transmitting, receiving and recording audio or ultrasonic signals, and capable of converting the signals into digital data, and performing digital signal processing. Voice pattern(s) and user(s) information of one or more authorized user(s) are recorded and stored on the authentication device. User(s) identification is verified by inputting to the authentication device a vocal identification signal from a user, and comparing the voice pattern of the vocal identification signal with the recorded voice pattern(s) of the authorized user(s), and if a match is detected issuing an indication that the user is identified as an authorized user.

Digital control with improved performance for boost power factor correction circuits

Abstract: In this paper, an approach for the design of a digital controller for a PFC pre-regulator is proposed. The controller is modified to account for large control periods and computational delays, and can therefore be implemented on processors with few available computational resources. Results show that, even with a very low control rate, system specifications can be met using the proposed technique.

Methods and systems for digitally processing optical data signals

Abstract: Digital signal processing based methods and systems for receiving electrical and/or optical data signals include electrical receivers, optical receivers, parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a single path receiver. Alternatively, the present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.

Fault classification based on wavelet transforms

Abstract: This paper presents a new approach to fault classification on transmission lines for high speed protective relaying. The scheme is based on the use of wavelet transform and implementation of digital signal processing concepts. It uses samples from the three line currents. The data window is 6 samples based on 10 kHz sampling rate. The new technique is tested on data simulated on EMTP for the 11 types of faults at different fault locations, different fault resistances, different fault inception angles, and different system parameters. The test results showed that the proposed algorithm offers a fast and secure technique for fault classification in power systems. The paper presents the basics of the wavelet transforms technique in power systems terminology and illustrates its use in the new algorithm.

Multirate Systems: Design and Applications

Abstract: Book Description Digital signal processing is an area of science and engineering that has been developed rapidly over the past years. This rapid development is the result of the significant advances in digital computer technology and integrated circuits fabrication. Many of the signal processing tasks conventionally performed by analog means, are realized today by less expensive and often more reliable digital hardware. Multirate Systems: Design and Applications addresses the rapid development of multirate digital signal processing and how it is complemented by the emergence of new applications.

A DSP based controller for power factor correction (PFC) in a rectifier circuit

Abstract: In this paper a digital signal processor (DSP) based power factor correction (PFC) scheme is presented. A dual-loop controller is designed to control the average input AC current as well as DC bus voltage. The DSP controller is implemented and tested. Design methodologies and trade-offs such as discrete-time implementation methods are also presented.

Filter banks in digital communications

Abstract: Digital signal processing has played a key role in the development of telecommunication systems over the last two decades. In recent years digital filter banks have been occupying an increasingly important role in both wireless and wireline communication systems. In this paper we review some of these applications of filter banks with special emphasis on discrete multitone modulation which has had an impact on high speed data communication over the twisted pair telephone line. We also review filter bank precoders which have been shown to be important for channel equalization applications.

Acoustical proximity detection for mobile terminals and other devices

Abstract: A method and a device for detecting if an object is in proximity to the device, wherein sound (audio) transducers already found in the device are used to realize the proximity detection function, along with digital signal processing or equivalent means. The audio transducers are preferably those designed for use with human hearing and speaking capabilities in the range of about 20 Hz to about 20 kHz, and need not be specially designed transducers. The method includes steps of generating a measurement signal; driving an output acoustic transducer of the device with the measurement signal; monitoring an input acoustic transducer of the device to detect the measurement signal; and determining that an object is in proximity to the device based on a detected alteration of the measurement signal. The device may comprise a mobile telephone, such as a cellular telephone, or a personal communicator. When the device includes a mobile telephone, the step of determining can be used to verify that a handsfree mode of operation can be entered, and/or to set a volume of a signal driving a speaker, and/or to select, modify, or tune an audio processing technique. The step of determining can also be used to automatically enter a handset mode of operation from a handsfree mode of operation. The steps of monitoring and determining include steps of operating plural adaptive filters in parallel on the same input data, with different step sizes, for generating first and second impulse response estimates, respectively, and comparing a difference between the first and second impulse response estimates to a threshold.

Digital signal processing method and system thereof for precision orientation measurements

Abstract: The present invention provides a digital signal processing method and system thereof for producing precision platform orientation measurements and local Earth's magnetic measurements by measuring threes axes gravity acceleration digital signals by an acceleration producer, detecting Earth's magnetic field vector measurement by an Earth's magnetic field detector to achieve digital three-axes Earth's magnetic field vector signals, and producing pitch, roll, and heading angles using said three-axes gravity acceleration digital signals and said digital three-axes Earth magnetic field vector signals by a Digital Signal Processor (DSP) chipset.

Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Abstract: In this paper, we first present a reconfigurable architecture template for low-power digital signal processing, and then an energy conscious design methodology to bridge the algorithm to architecture gap. The energy efficiency of such an architecture and the effectiveness of the methodology are demonstrated in case study implementations targeting baseband voice processing and digital signal processing.

System and method for high speed communications using digital signal processing

Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed In one implementation precoding is performed on signals transmitted over an optical channel In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs

System for integrating digital control with common substrate display devices

Abstract: A method of manufacturing a display module, including the steps of: providing a substrate; and forming on the substrate using the same manufacturing process an image display having an array of addressable display pixels and pixel driver circuitry responsive to control signals and image data for driving the pixels; and a digital signal processing circuit having an input interface over which image data and control signals are received; a frame buffer for storing image data and from which image data is read during a display refresh; a display matrix driver circuit for receiving image data from the frame buffer and supplies control signals to the pixel driver circuitry; a control circuit for coordinating storage, retrieval, and display operations, such that the display module is capable of display refresh independently of external control; and an image processing circuit for improving the visual perception of the displayed image