Showing papers on "Digital signal processing published in 2002"

Adaptive blind signal and image processing

Abstract: Find the secret to improve the quality of life by reading this adaptive blind signal and image processing. This is a kind of book that you need now. Besides, it can be your favorite book to read after having this book. Do you ask why? Well, this is a book that has different characteristic with others. You may not need to know who the author is, how well-known the work is. As wise word, never judge the words from who speaks, but make the words as your good value to your life.

Dafx : Digital Audio Effects

Abstract: From the Publisher: Digital Audio Effects stand for the highest possible sound quality and the finest level of control in the modern world of music and sound. Digital Audio Effects (DAFX) is also the name chosen for the European Research Project COST G6 which investigates the use of digital signal processing, its application to sounds, and its musical use designed to put effects on a sound. The aim of the project and this book is to present the main fields of digital audio effects. It systematically introduces the reader to digital signal processing concepts as well as software implementations using MATLAB. Highly acclaimed contributors analyse the latest findings and developments in filters, delays, modulators, and time-frequency processing of sound. Features include: Chapters on time-domain, non-linear, time-segment, time-frequency, source-filter, spectral, bitstream signal processing; spatial effects, time and frequency warping and control of DAFX. MATLAB implementations throughout the book illustrate essential DSP algorithms for sound processing. Accompanying website with sound examples available The approach of applying digital signal processing to sound will appeal to sound engineers as well as to researchers and engineers in the field of signal processing. DAFX - Digital Audio Effects features contributions from Daniel Arfib, Xavier Amatrain, Jordi Bonada, Giovanni de Poli, Pierre Dutilleux, Gianpaolo Evangelista, Florian Keiler, Alex Loscos, Davide Rocchesso, Mark Sandler, Xavier Serra, and Todor Todoroff.

Method and apparatus for audio-visual speech detection and recognition

Abstract: Techniques for providing speech recognition comprise the steps of processing a video signal associated with an arbitrary content video source, processing an audio signal associated with the video signal, and recognizing at least a portion of the processed audio signal, using at least a portion of the processed video signal, to generate an output signal representative of the audio signal.

Quantization Noise: Roundoff Error in Digital Computation, Signal Processing, Control, and Communications

Abstract: If you are working in digital signal processing, control or numerical analysis, you will find this authoritative analysis of quantization noise (roundoff error) invaluable Do you know where the theory of quantization noise comes from, and under what circumstances it is true? Get answers to these and other important practical questions from expert authors, including the founder of the field and formulator of the theory of quantization noise, Bernard Widrow The authors describe and analyze uniform quantization, floating-point quantization, and their applications in detail Key features include: Analysis of floating point round off Dither techniques and implementation issues analyzed Offers heuristic explanations along with rigorous proofs, making it easy to understand 'why' before the mathematical proof is given

Digital Signal Processing: System Analysis and Design

Abstract: From the Publisher: Digital signal processing lies at the heart of the communications revolution and is an essential element of key technologies such as mobile phones and the Internet. This book covers all the major topics in digital signal processing (DSP) design and analysis, supported by MATLAB examples and other modeling techniques. The authors explain clearly and concisely why and how to use digital signal processing systems; how to approximate a desired transfer function characteristic using polynomials and ratios of polynomials; why an appropriate mapping of a transfer function onto a suitable structure is important for practical applications; and how to analyze, represent, and explore the trade-off between time and frequency representation of signals. An ideal textbook for students, it will also be a useful reference for engineers working on the development of signal processing systems.

CMOS Mixed-Signal Circuit Design

Abstract: The power of mixed-signal circuit designs, and perhaps the reason they are replacing analog-only designs in the implementation of analog interfaces, comes from the marriage of analog circuits with digital signal processing This book builds on the fundamental material in the author's previous book, CMOS: Circuit Design, Layout, and Simulation, to provide a solid textbook and reference for mixed-signal circuit design The coverage is both practical and in-depth, integrating experimental, theoretical, and simulation examples to drive home the why and the how of doing mixed-signal circuit design Some of the highlights of this book include: (1) A practical/theoretical approach to mixed-signal circuit design with an emphasis on oversampling techniques; (2) An accessible and useful alternative to hard-to-digest technical papers without losing technical depth; (3) Coverage of delta-sigma data converters, custom analog and digital filter design, design with submicron CMOS processes, and practical at-the-bench deadbug prototyping techniques; (4) Hundreds of worked examples and questions covering all areas of mixed-signal circuit design

PID controller modifications to improve steady-state performance of digital controllers for buck and boost converters

Abstract: The sensitivity of the analog-to-digital converter and inherent time delay in a digital controller can degrade the steady-state performance of a DC-DC power converter. Analog PID controllers were designed for prototype buck and boost converters and then implemented on a TI DSP. Three modifications to the digital PID controllers were investigated to improve their steady-state performance. The modifications were a dead zone, an averaging digital filter and two sets of gains. The digital controller monitors the output voltage error to determine if a modification should be employed to calculate the next duty cycle. Experimental results from both prototype converters indicates that a stable and accurate steady-state response can be obtained while maintaining a good transient response.

Compression depth estimation for CPR quality assessment using DSP on accelerometer signals

Abstract: Chest compression is a vital part of cardiopulmonary resuscitation (CPR). This paper demonstrates how the compression depth can be estimated using the principles of inertia navigation. The proposed method uses accelerometer sensors, one placed on the patient's chest, the other beside the patient. The acceleration-to-position conversion is performed using discrete-time digital signal processing (DSP). Instability problems due to integration are combated using a set of boundary conditions. The proposed algorithm is tested on a mannequin in harsh environments, where the patient is exposed to external forces as in a boat or car, as well as improper sensor/patient alignment. The overall performance is an estimation depth error of 4.3 mm in these environments, which is reduced to 1.6 mm in a regular, flat-floor controlled environment.

Self-calibrating, digital, large format camera with single or multiple detector arrays and single or multiple optical systems

Abstract: Large format, digital camera systems (10, 100, 150, 250, 310) expose single detector arrays 20 with multiple lens systems (12, 14, 16, 18) or multiple detector arrays (104, 106, 108, 110, 112, 114, 116, 118, 120, 152, 162, 172, 182, 252, 262, 272, 282, 322, 324) with one or more single lens systems (156, 166, 176, 186) to acquire sub-images of overlapping sub-areas of large area objects. The sub-images are stitched together to form a large format, digital, macro-image (80, 230', 236', 238', 240'), which can be colored. Dampened camera carrier (400) and accelerometer (404) signals with double-rate digital signal processing (306, 308) are used.

Digital audio signal filtering mechanism and method

Abstract: Essentially all of the processing parameters which control processing of a source audio signal to produce an encoded audio signal are stored in an audio processing profile. Multiple audio processing profiles are stored in a processing profile database such that specific combinations of processing parameters can be retrieved and used at a later time. Audio processing profiles are organized according to specific delivery bandwidths such that a sound engineer can quickly and efficiently encode audio signals for each of a number of distinct delivery media. Synchronized A/B switching during playback of various encoded audio signals allows the sound engineer to detect nuances in the sound characteristics of the various encoded audio signals.

Chess : Retargetable Code Generation for Embedded DSP Processors

Abstract: This chapter introduces Chess, a retargetable code generation environment for fixedpoint DSP processors. Chess addresses a range of commercial as well as applicationspecific processors, which are increasingly being used for embedded applications in telecommunications, speech and audio processing. Chess is based on a mixed behavioural/structural processor representation model, which can account for many architectural peculiarities that are typical for fixed-point DSP processors. In addition, the code generator is employing a number of efficient optimisation techniques. These features result in highly optimal machine code.

Complete analysis and comparative study of digital modulation techniques for dual three-phase AC motor drives

Abstract: The main goal of the paper is to perform a complete analysis and a comparative study of different digital pulsewidth modulation (PWM) techniques for dual three-phase induction machine drives. Six different digital PWM strategies are considered: four of them are present in the literature, the other two have been introduced by the authors in this paper. The comparison between the modulation strategies is based on several criteria: current harmonic minimisation, hardware and software implementation complexity with low cost fixed-point DSP platforms. Simulation results are provided to emphasize the advantages and disadvantages of each method. Experimental tests have been carried out to validate the most promising strategy which gives satisfactory results in terms of current harmonic minimisation and low implementation complexity.

Image processor circuits, systems, and methods

Abstract: An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

Method for time aligning audio signals using characterizations based on auditory events

Abstract: A method for time aligning audio signal, wherein one signal has been derived from the other or both have been derived from another signal, comprises deriving reduced-information characterizations of the audio signals, auditory scene analysis. The time offset of one characterization with respect to the other characterization is calculated and the temporal relationship of the audio signals with respect to each other is modified in response to the time offset such that the audio signals are coicident with each other. These principles may also be applied to a method for time aligning a video signal and an audio signal that will be subjected to differential time offsets.

Method and apparatus for converting a low dynamic range analog signal to a large dynamic range floating-point digital representation

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level S s to corresponding digital representations at several sub-conversion times t=T 2 >T 1 , t=T 3 >T 2 , . . . t=T M >T M−1 , where T M ≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than S s at time t=T.

Methods and systems for dsp-based receivers

Abstract: Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.

Classification of washing machines vibration signals using discrete wavelet analysis for feature extraction

Abstract: Wavelets provide a powerful tool for nonstationary signal analysis. In vibration monitoring, the occurrence of occasional transient disturbances makes the recorded signal nonstationary, especially during the start-up of an engine. Through the wavelet analysis, transients can be decomposed into a series of wavelet components, each of which is a time-domain signal that covers a specific octave frequency band. Disturbances of small extent (duration) are amplified relative to the rest of the signal when projected to similar size wavelet bases and, thus, they can be easily detected in the corresponding frequency band. This paper presents a new method for extracting features in the wavelet domain and uses them for classification of washing machines vibration transient signals. The discrete wavelet transform (DWT), in conjunction with statistical digital signal processing techniques, is used for feature extraction. The Karhunen Loeve transform (KLT) is used for feature reduction and decorrelation of the feature vectors. The Euclidean, Mahalanobis, and Bayesian distance classifiers, the learning vector quantization (LVQ) classifier, and the fuzzy gradient classifier are used for classification of the resulting feature space. Classification results are illustrated and compared for the rising part of vibration velocity signals of a variety of real washing machines with various defects.

The ALTRO chip: a 16-channel A/D converter and digital processor for gas detectors

Abstract: The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed. compressed and stored in a multi-acquisition memory. The Analogue-to-Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40 MHz. After digitisation, a pipelined hardwired processor is able to remove from the input signal a wide range of systematic and non- systematic perturbations, related to the non-ideal behaviour of lite detector, temperature variation of the electronics, environmental noise, etc. Moreover. the processor is able to suppress the signal tail within 1 /spl mu/s after the pulse peak with 0.1% accuracy thus narrowing the pulses to improve their identification. The signal is then compressed by removing all data below a programmable threshold, except for a specified number of pre- and post-samples around each peak. This produces non-zero data packets. Eventually, each data packet is marked with its time stamp and size - so that the original data can be reconstructed afterwards and stored in lite multi-acquisition memory that has a readout bandwidth of 300 Mbyte/sec. This paper addresses the algorithms of lite implemented digital functions and the performance of the ALTRO chip on measured data.

Design of a plug-in type repetitive controller for periodic inputs

Abstract: This paper presents some practical design criteria for a plug-in type repetitive controller to achieve good tracking performance within a specified frequency range. Upper and lower bounds of the repetitive controller parameters that ensure the stability and the desired performance are derived. It has been found that the decay rate of the tracking error due to periodic inputs is related to the peak value of a defined regeneration spectrum function. The control performance of the present method is evaluated in an experimental software cam system, which needs periodic linear motions, where the real-time control algorithms are implemented using a floating-point digital signal processor (DSP). Both computer simulation and experimental results are presented to illustrate the effectiveness of the proposed repetitive controller design.

Radio base station receiver having digital filtering and reduced sampling frequency

Abstract: A station for processing a first signal which can be generated by a mobile terminal and belongs to a plurality of signals for mobile radio communications networks. The stations include an input able to receive from an antenna the first signal associated with a first band and at least one adjacent signal of said plurality associated with a second band adjacent to that of the first signal; a processing stage for generating from the first digital signal at a first sampling frequency, this first digital signal including a useful spectral content of the first signal and an interfering spectral content associated with the adjacent signal; a digital filter for processing the first digital signal, attenuating the interfering spectral content, and for providing a filtered digital signal including at least part of the useful special content sampled at a second sampling frequency less than the first sampling frequency and an electro-optical converter for generating from the filtered digital signal electromagnetic radiation to be transmitted on a waveguide.

Digital filter synthesis based on an algorithm to generate all minimal signed digit representations

Abstract: In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters based on the MSD representation. The hardware complexity of a digital signal processing system is dependent on the number system used for the implementation. Although the canonical signed digit (CSD) representation is widely employed, as it is unique and guarantees the minimal number of nonzero digits for a constant, the MSD representation provides multiple representations that have the same number of nonzero digits as the CSD representation. The proposed filter synthesis algorithm utilizes this redundancy of the MSD representation to make common subexpressions, as many as possible, leading to smaller filters. By applying the proposed algorithm to the hardware synthesis of finite impulse response filters, the authors obtained multiplier blocks that are 7% smaller than those generated from the CSD representation.

A new FPGA/DSP-based parallel architecture for real-time image processing

Abstract: In this article, we present a new reconfigurable parallel architecture oriented to video-rate computer vision applications. This architecture is structured with a two-dimensional (2D) array of FPGA/DSP-based reprogrammable processors Pij. These processors are interconnected by means of a systolic 2D array of FPGA-based video-addressing units which allow video-rate links between any two processors in the net to overcome the associated restrictions in classic crossbar systems such as those which occur with butterfly connections. This architecture has been designed to deal with parallel/pipeline procedures, performing operations which handle various simultaneous input images, and cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. This proposed open architecture allows the host to deal with final high-level interpretation tasks. The exchange of information between the linked processors Pij of the 2D net lies in the transfer of complete images, pixel by pixel, at video-rate. Therefore, any kind of processor satisfying such a requirement can be integrated. Furthermore, the whole architecture has been designed host-independent.

A calibration procedure for a digital instrument for electric power quality measurement

Abstract: The measurement of power quality is becoming an impelling need in a deregulated electricity market where the sources producing distortion and disturbances are steadily in creasing in number and power. The instruments for power quality measurement are based on complex digital processing of the input signals, whose waveforms are highly variable. The calibration of this kind of instruments is therefore an open topic, especially when the uncertainty propagation through the digital signal processing (DSP) algorithm is concerned. This paper proposes an innovative procedure, based on the Monte Carlo method. Starting from the determination of the probability density function of the uncertainty contribution of every device from the signal input stage to the analog-to-digital conversion stage, this procedure estimates the probability density function of the measurement results and the measurement standard uncertainty as the standard deviation associated with this function. The result of the experimental work done on a prototype of a power quality measurement instrument is reported.

A novel smart antenna system implementation for broad-band wireless communications

Abstract: A novel design of smart antenna system with adaptive beamforming capability is introduced for broad-band wireless communication. To achieve high data throughput of the multi-antenna system, a parallel analog-digital (A/D) signal processing scheme is proposed. The essential idea is to realize the real-time beamforming using heterodyne RF and IF circuitry. The bottleneck of digital signal processor (DSP) I/O and processing speed is thus relieved, while the advanced signal processing capability of the DSP chip is utilized. Based on this idea, a 5.8 GHz smart antenna receiver is implemented. Various experiments are carried out to examine the direction of arrival (DOA) estimation, beam synthesis, and bit error rate (BER) performances of the system. A 20-Mb/s data throughput using binary phase shift keying (BPSK) modulation is demonstrated for this eight-element adaptive array.

A "digital" 6-bit ADC in 0.25-μm CMOS

Abstract: Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25~ digital CMOS process occupies 1.2mm2 and dissipates llOmW from a 2.2V supply at 300Ms/s.

Data-aided approach to I/Q mismatch and DC offset compensation in communication receivers

Abstract: A digital signal processing technique for compensating both the I/Q mismatch and the DC offset in communication receivers is derived with an emphasis on direct-conversion architectures. The I/Q mismatch and DC offset are estimated in a least-squares sense using a training sequence. Also, a group of training sequences that minimizes the mean square error of the estimate is determined. The advantages of the proposed technique are demonstrated through computer simulation.

A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits

Abstract: An area-efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). Several prototypes were fabricated in a triple-metal 3.3-V 0.35-/spl mu/m CMOS process, and were demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks at a clock rate of 20 MHz (limited by our experimental setup). Designed for 8 bits of quantization, a spurious-free dynamic range (SFDR) of 65 dB at 500 KHz and 61 dB at Nyquist (20.001 MHz) was demonstrated using our prototypes. High-frequency narrow-band signals (extending into the gigahertz range) have been captured through subsampling and the use of a high-bandwidth front-end sampling network. Similarly, circuit phenomena that are broadband in nature were measured by using a delayed-clock subsampling mechanism in which the digitizer sample clock is consistently delayed over multiple runs of the periodic test signal. Delaying the clock is performed using a voltage-controlled delay line tuned by a self-biased delay-locked loop, which allowed for a timing resolution of about one gate delay (/spl sim/200 ps). The proposed test core occupies an area equivalent to only about 7000 standard-cell 2-input NAND gates.