Showing papers on "Digital signal processing published in 2004"

Implementation issues in spectrum sensing for cognitive radios

Abstract: There are new system implementation challenges involved in the design of cognitive radios, which have both the ability to sense the spectral environment and the flexibility to adapt transmission parameters to maximize system capacity while coexisting with legacy wireless networks. The critical design problem is the need to process multigigahertz wide bandwidth and reliably detect presence of primary users. This places severe requirements on sensitivity, linearity and dynamic range of the circuitry in the RF front-end. To improve radio sensitivity of the sensing function through processing gain we investigated three digital signal processing techniques: matched filtering, energy detection and cyclostationary feature detection. Our analysis shows that cyclostationary feature detection has advantages due to its ability to differentiate modulated signals, interference and noise in low signal to noise ratios. In addition, to further improve the sensing reliability, the advantage of a MAC protocol that exploits cooperation among many cognitive users is investigated.

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

Abstract: We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.

Coherent detection method using DSP for demodulation of signal and subsequent equalization of propagation impairments

Abstract: A new approach to coherent detection is demonstrated which achieves the same high sensitivity as homodyne detection but without the need to phase lock the local oscillator laser. In addition, 1470 ps/nm of chromatic dispersion is compensated with zero net penalty by electronic domain equalization, a result which has not been achieved before because zero-penalty equalization is not possible after direct detection. The method proposes the use of high-speed digital signal processing technology, and the experimental results are obtained using burst-mode sampling followed by offline signal processing.

Multirate Signal Processing for Communication Systems

Abstract: Multirate Signal Processing for Communication Systems: Current Practice and Next Generation Techniques fredric j harrisMultirate signal processing can reduce costs and improve performance in applications ranging from laboratory instruments to cable modems, wireless systems, and consumer entertainment products. This book offers the first systematic, clear, and intuitive introduction to multirate signal processing for working engineers and system designers.The author uses extensive examples and figures to illuminate a wide range of multirate techniques, from basic resampling to leading-edge cascade and multiple-stage filter structures. Along the way, he draws on extensive research and consulting experience to introduce processing itricksi shown to maximize performance and efficiency.Coverage includes: Effective sampling and resampling in time and frequency domains Relationships between IIR Filter specifications and filter length (taps) Window design and equal-ripple (Remez) design techniques Square-Root Nyquist and Half Band Filters, including new design enhancements Polyphase IIR Filters: up-sampling, down-sampling, and cascade up-down sampling Polyphase interpolators and filters that perform arbitrary sample rate change Dyadic Half Band Filters, including quadrature mirror and IIR Filters Polyphase Channelizers, including M-path modulators, demodulator channel banks, simultaneous interpolation, and channel bank formation Comprehensive coverage of recursive all-pass filtersoa topic never before covered in this detail Comparisons with traditional DSP design techniques Extensive applications coverage throughout

From frequency to quefrency: a history of the cepstrum

Abstract: The idea of the log spectrum or cepstral averaging has been useful in many applications such as audio processing, speech processing, speech recognition, and echo detection for the estimation and compensation of convolutional distortions. To suggest what prompted the invention of the term cepstrum, this article narrates the historical and mathematical background that led to its discovery. The computations of earlier simple echo representations have shown that the spectrum representation domain results does not belong in the frequency or time domain. Bogert et al. (1963) chose to refer to it as quefrency domain and later termed the spectrum of the log of a time waveform as the cepstrum. The article also recounts the analysis of Al Oppenheim in relation to the cepstrum. It was in his theory for nonlinear signal processing, referred to as homomorphic systems, that the realization of the characteristic system of homomorphic convolution was reminiscent of the cepstrum. To retain both the relationship to the work of Bogart et al. and the distinction, the term power cepstrum was eventually applied to the nonlinear mapping in homomorphic deconvolution . While most of the terms in the glossary have faded into the background, the term cepstrum has survived and has become part of the digital signal processing lexicon.

Barcode readers using the camera device in mobile phones

Abstract: This paper shows new algorithms and the implementations of image reorganization for EAN/QR barcodes in mobile phones. The mobile phone system used here consists of a camera, mobile application processor, digital signal processor (DSP), and display device, and the source image is captured by the embedded camera device. The introduced algorithm is based on the code area found by four corners detection for 2D barcode and spiral scanning for 1D barcode using the embedded DSP. This algorithm is robust for practical situations and the DSP has good enough performance for the real-time recognition of the codes. The performance of our image processing is 66.7 frames/sec for EAN code and 14.1 frames/sec for QR code image processing, and this is sufficient performance for practical use. The released mobile phone had performance of 5-10 frames/sec including OS and subsystem overheads.

Predictive current control of voltage-source inverters

Abstract: A new predictive current controller for a voltage-source inverter is presented in this paper. Practical aspects of realizing the new controller in a system with a digital signal processor (DSP) are considered. Delays introduced by measurements are considered and an improved algorithm with one-period prediction of current is presented. The controller was realized in an experimental system with DSP and field-programmable gate array circuits. Results of the simulations and experiments are presented.

A digital power factor correction (PFC) control strategy optimized for DSP

Abstract: A predictive algorithm for digital control power factor correction (PFC) is presented in this paper. Based on this algorithm, all of the duty cycles required to achieve unity power factor in one half line period are calculated in advance by digital signal processors (DSP). A boost converter controlled by these precalculated duty cycles can achieve sinusoidal current waveform. One main advantage is that the digital control PFC implementation based on this control strategy can operate at a high switching frequency which is not directly dependent on the processing speed of DSP. Input voltage feed-forward compensation makes the output voltage insensitive to the input voltage variation and guarantees sinusoidal input current even if the input voltage is distorted. A prototype of boost PFC controlled by a DSP evaluation board was set up to implement the proposed predictive control strategy. Both the simulation and experimental results show that the proposed predictive strategy for PFC achieves near unity power factor.

Understanding Digital Signal Processing (2nd Edition)

Abstract: Amazon.com's top-selling DSP book for 5 straight years-now fully updated!Real-world DSP solutions for working professionals!Understanding Digital Signal Processing, Second Edition is quite simply the best way for engineers, and other technical professionals, to master and apply DSP techniques. Lyons has updated and expanded his best-selling first edition-building on the exceptionally readable coverage that made it the favorite of professionals worldwide.This book achieves the perfect balance between theory and practice, making DSP accessible to beginners without ever oversimplifying it. Comprehensive in scope and gentle in approach, keeping the math at a tolerable level, this book helps readers thoroughly grasp the basics and quickly move on to more sophisticated techniques.This edition adds extensive new coverage of quadrature signals for digital communications; recent improvements in digital filtering; and much more. It also contains more than twice as many "DSP Tips and Tricks"... including clever techniques even seasoned professionals may have overlooked. Down-to-earth, intuitive, and example-rich, with detailed numerical exercises Stresses practical, day-to-day DSP implementations and problem-solving All-new quadrature processing coverage includes easy-to-understand 3D drawings Extended coverage of IIR filters; plus frequency sampling, interpolated FIR filters New coverage of multirate systems; including both polyphase and cascaded integrator-comb FIR filters Coverage includes: periodic sampling, DFT, FFT, digital filters, discrete Hilbert transforms, sample rate conversion, quantization, signal averaging, and more

An introduction to statistical signal processing

Abstract: This volume describes the essential tools and techniques of statistical signal processing. At every stage, theoretical ideas are linked to specific applications in communications and signal processing. The book begins with an overview of basic probability, random objects, expectation, and second-order moment theory, followed by a wide variety of examples of the most popular random process models and their basic uses and properties. Specific applications to the analysis of random signals and systems for communicating, estimating, detecting, modulating, and other processing of signals are interspersed throughout the text.

Computers As Components: Principles Of Embedded Computing System Design

Abstract: Computers as Components: Principles of Embedded Computing System Design, 3e, presents essential knowledge on embedded systems technology and techniques. Updated for today's embedded systems design methods, this edition features new examples including digital signal processing, multimedia, and cyber-physical systems. Author Marilyn Wolf covers the latest processors from Texas Instruments, ARM, and Microchip Technology plus software, operating systems, networks, consumer devices, and more. Like the previous editions, this textbook: * Uses real processors to demonstrate both technology and techniques* Shows readers how to apply principles to actual design practice* Stresses necessary fundamentals that can be applied to evolving technologies and helps readers gain facility to design large, complex embedded systems Updates in this edition include: * Description of cyber-physical systems: physical systems with integrated computation to give new capabilities* Exploration of the PIC and TI OMAP processors* High-level representations of systems using signal flow graphs* Enhanced material on interprocess communication and buffering in operating systems* Design examples include an audio player, digital camera, cell phone, and more * Description of cyber-physical systems: physical systems with integrated computation to give new capabilities* Exploration of the PIC and TI OMAP multiprocessors* High-level representations of systems using signal flow graphs* Enhanced material on interprocess communication and buffering in operating systems* Design examples include an audio player, digital camera, cell phone, and more

Reliable low-power digital signal processing via reduced precision redundancy

Abstract: In this paper, we present a novel algorithmic noise-tolerance (ANT) technique referred to as reduced precision redundancy (RPR). RPR requires a reduced precision replica whose output can be employed as the corrected output in case the original system computes erroneously. When combined with voltage overscaling (VOS), the resulting soft digital signal processing system achieves up to 60% and 44% energy savings with no loss in the signal-to-noise ratio (SNR) for receive filtering in a QPSK system and the butterfly of fast Fourier transform (FFT) in a WLAN OFDM system, respectively. These energy savings are with respect to optimally scaled (i.e., the supply voltage equals the critical voltage V/sub dd-crit/) present day systems. Further, we show that the RPR technique is able to maintain the output SNR for error rates of up to 0.09/sample and 0.06/sample in an finite impulse response filter and a FFT block, respectively.

Algorithms for audio watermarking and steganography

Abstract: Broadband communication networks and multimedia data available in a digital format opened many challenges and opportunities for innovation. Versatile and simple-to-use software and decreasing prices of digital devices have made it possible for consumers from all around the world to create and exchange multimedia data. Broadband Internet connections and near error-free transmission of data facilitate people to distribute large multimedia files and make identical digital copies of them. A perfect reproduction in digital domain have promoted the protection of intellectual ownership and the prevention of unauthorized tampering of multimedia data to become an important technological and research issue. Digital watermarking has been proposed as a new, alternative method to enforce intellectual property rights and protect digital media from tampering. Digital watermarking is defined as imperceptible, robust and secure communication of data related to the host signal, which includes embedding into and extraction from the host signal. The main challenge in digital audio watermarking and steganography is that if the perceptual transparency parameter is fixed, the design of a watermark system cannot obtain high robustness and a high watermark data rate at the same time. In this thesis, we address three research problems on audio watermarking: First, what is the highest watermark bit rate obtainable, under the perceptual transparency constraint, and how to approach the limit? Second, how can the detection performance of a watermarking system be improved using algorithms based on communications models for that system? Third, how can overall robustness to attacks to a watermark system be increased using attack characterization at the embedding side? An approach that combined theoretical consideration and experimental validation, including digital signal processing, psychoacoustic modeling and communications theory, is used in developing algorithms for audio watermarking and steganography. The main results of this study are the development of novel audio watermarking algorithms, with the state-of-the-art performance and an acceptable increase in computational complexity. The algorithms' performance is validated in the presence of the standard watermarking attacks. The main technical solutions include algorithms for embedding high data rate watermarks into the host audio signal, using channel models derived from communications theory for watermark transmission and the detection and modeling of attacks using attack characterization procedure. The thesis also includes a thorough review of the state-of-the-art literature in the digital audio watermarking.

Real-time video analysis on an embedded smart camera for traffic surveillance

Abstract: A smart camera combines video sensing, high-level video processing and communication within a single embedded device. Such cameras are key components in novel surveillance systems. This paper reports on a prototyping development of a smart camera for traffic surveillance. We present its scalable architecture comprised of a CMOS sensor, digital signal processors (DSP), and a network processor. We further discuss the mapping of high-level video processing algorithms to embedded DSP-based platforms and identify typical pitfalls for the porting of software from desktops to embedded platforms. Our mapping strategies are demonstrated on an algorithm for automatic detection of stationary vehicles. This algorithm is migrated from a Matlab-based prototyping implementation to an embedded DSP implementation in our smart camera. Our implemented smart camera prototype streams the video data over an IP-network to a central monitoring station and is able to detect stationary vehicles and blocking cargo on highways within the required real-time constraints of six seconds.

A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process

Abstract: A discrete-time receiver architecture for a wireless application is presented. Analog signal processing concepts are used to directly sample the RF input at Nyquist rate. Maximum receiver sensitivity is -83dBm and the chip consumes a total of 41mA from a 1.575V internally regulated supply. The receiver is implemented in a 0.13/spl mu/m digital CMOS process.

Digital Signal Processing and Applications with the C6713 and C6416 DSK

Abstract: Preface.List of Examples.Programs/Files on Accompanying Disk.1. DSP Development System.2. Input and Output with the DSK.3. Architecture and Instruction Set of the C6x Processor.4. Finite Impulse Response Filters.5. Infinite Impulse Response Filters.6. Fast Fourier Transform.7. Adaptive Filters.8. Code Optimization.9. DSP/BIOS and RTDX Using MATLAB, Visual C++, Visual Basic, and LabVIEW.10. DSP Applications and Student Projects.Appendix A: TMS320C6x Instruction Set.Appendix B: Registers for Circular Addressing and Interrupts.Appendix C: Fixed-Point Considerations.Appendix D: Matlab Support Tools.Appendix E: Additional Support Tools.Appendix F: Fast Hartley Transform.Appendix G: Goertzel Algorithm.Appendix H: TMS320C6416 DSK.Appendix I: TMS320C6711 DSK.Index.

Systems and methods for digital processing of satellite communications data

Abstract: A digital payload for processing a sub-band spectrum received on an uplink beam at a communications satellite includes a digital channelizer, a digital switch matrix and a digital combiner. The digital channelizer divides the sub-band spectrum into a plurality of frequency slices that can be routed by the digital switch matrix to any of a number of receiving ports. A digital combiner receives the frequency slices and re-assembles them to form one or more output sub-bands for transmission on an output beam of the communications satellite. The digital payload may also include an embeddable digital regeneration module configured to demodulate some or all of the sub-band spectrum to extract a digital bitstream therefrom. The digital bitstream may be processed to implement code-based multiplexing, switching, access control, and other features.

Data hiding via phase manipulation of audio signals

Abstract: Data hiding in media, including images, video, and audio, and in data files is currently of great interest both commercially, mainly for the protection of copyrighted digital media, and to the government and law enforcement in the context of information system security and covert communications. We present a technique for inserting and recovering "hidden" data in audio files. The phase of chosen components of the host audio signal is manipulated in a way that may be detected by a receiver with the proper "key". Without the key, the hidden data is undetectable, both aurally and via blind digital signal processing attacks. The method described is both aurally transparent and robust and can be applied to both analog and digital audio signals, the latter including uncompressed as well as compressed audio file formats such as MP3.

Automated fixed-point data-type optimization tool for signal processing and communication systems

Abstract: A tool that automates the floating-point to fixed-point conversion (FFC) process for digital signal processing systems is described. The tool automatically optimizes fixed-point data types of arithmetic operators, including overflow modes, integer word lengths, fractional word lengths, and the number systems. The approach is based on statistical modeling, hardware resource estimation and global optimization based on an initial structural system description. The basic technique exploits the fact that the fixed point realization is a weak perturbation of the floating point realization which allows the development of a system model which can be used in the optimization process.

Applications of cascading DSP slices

Abstract: In one embodiment an IC is disclosed which includes a plurality of cascaded digital signal processing slices, wherein each slice has a multiplier coupled to an adder via a multiplexer and each slice has a direct connection to an adjoining slice; and means for configuring the plurality of digital signal processing slices to perform one or more mathematical operations, via, for example, opmodes. This IC allows for the implementation of some basic math functions, such as add, subtract, multiply and divide. Many other applications may be implemented using the one or more DSP slices, for example, accumulate, multiply accumulate (MACC), a wide multiplexer, barrel shifter, counter, and folded, decimating, and interpolating FIRs to name a few.

Z-transform implementation of digital watermarks

Abstract: Z-transform calculations may be used to encode (and/or decode) carrier signal independent data (e.g., digital watermarks) to a digital sample stream. Deterministic and non-deterministic components of a digital sample stream signal may be analyzed for the purposes of encoding carrier signal independent data to the digital sample stream. The carrier signal independent data may be encoded in a manner such that it is restricted or concentrated primarily in the non-deterministic signal components of the carrier signal. The signal components can include a discrete series of digital samples and/or a discreet series of carrier frequency sub-bands of the carrier signal. Z-transform calculations may be used to measure a desirability of particular locations and a sample stream in which to encode the carrier signal independent data.

Equalization strategy for dual-polarization optical transport system

Abstract: A method is provided for an equalization strategy for compensating channel distortions in a dual-polarization optical transport system wherein the received signal includes a complex signal of a first transmitted polarization component and a complex signal of a second transmitted polarization component. In a first step, a blind self-recovery mode used a blind adaptation algorithm in calculating and modifying multiple complex equalizer transfer function coefficients to enable recovery of only the complex signal of the first transmitted polarization component. By recovering only a single polarization component in the first step the degenerate case of recovering only a single transmitted signal at both polarization component outputs of an equalizer is prevented. In a second step, equalization is performed in a training mode for calculating and modifying the multiple complex equalizer transfer function coefficients to enable recovery of the complex signals of the first and second transmitted polarization components. In a third step, equalization is performed in a data directed mode for continuing to calculate and modify the multiple complex equalizer transfer function coefficients to ensure continued recovery of the complex signals of the first and second transmitted polarization components. The method is suited for a digital signal processing implementation in a coherent receiver when a modulation scheme used on a transmitted signal is quadriphase-shift keying (QPSK). In other embodiments, the method can be used with modulation schemes such as binary PSK, M-ary PSK where M>4, or Quadrature Amplitude Modulation (QAM).

Input data reuse in compiling window operations onto reconfigurable hardware

Abstract: Balancing computation with I/O has been considered as a critical factor of the overall performance for embedded systems in general and reconfigurable computing systems in particular. Data I/O often dominates the overall computation performance for window operation, which are frequently used in image processing, image compression, pattern recognition and digital signal processing. This problem is more acute in reconfigurable systems since the compiler must generate the data path and the sequence of operations. The challenge is to intelligently exploit data reuse on the reconfigurable fabric (FPGA) to minimize the required memory or I/O bandwidth while maximizing parallelism.In this paper, we present a compile-time approach to reuse data in window-based codes. The compiler, called ROCCC, first analyzes and optimizes the window operation in C. It then computes the size of the hardware buffer and defines three sets of data values for each window: the window set, the managed set and the killed set. This compile-time analysis simplifies the HDL code generation and improves the resulting hardware performance. We also discuss in-place window operations.

Acoustic Ranging in Resource-Constrained Sensor Networks.

Abstract: Fine-grained geographic localization of nodes is essential for an extensive range of distributed sensor applications. To compute geographic coordinates, localization algorithms commonly use pair-wise distance estimates between nodes. In this paper we present a noise tolerant acoustic ranging mechanism for wireless sensors that employs digital signal processing techniques on standard MICA hardware. We describe how noise canceling, digital filtering and peak detection can be applied to meet the severe resource constraints of the platform, yet yielding average range estimation errors below 10cm independently from the actual node-to-node

LINC power transmitter

Abstract: A linear amplification with nonlinear components (LINC) power transmitter is provided. The LINC power transmitter includes a digital signal processing unit which controls the LINC power transmitter; a frequency modulation unit which modulates or converts a digital signal output from the digital signal processing unit into a radio-frequency (RF) signal; a signal amplification unit which amplifies the RF signal output from the frequency modulation unit using a gain amplifier and a power amplification module; and a direct current/direct current (DC/DC) conversion unit which controls bias of the power amplification module. Here, the DC/DC conversion unit controls a base bias and/or a collect bias of the power amplification module, and the power amplification module operates in saturation.

DSP implementation of power measurements according to the IEEE trial-use standard 1459

Abstract: A digital signal processor (DSP) based prototype platform used to support advanced power measuring algorithms is presented. For this study, the definitions proposed in the new IEEE Standard 1459-2000 are considered. The general structure of the system and the impact of the software implementation are discussed. Experimental measurement results from tests performed on a low voltage distribution grid are included.