Showing papers on "Digital signal processing published in 2005"

Fundamentals of Radar Signal Processing

Abstract: This detailed guide clearly and concisely presents radar digital signal processing for both practicing engineers and engineering students. This revised edition of Fundamentals of Radar Signal Processing provides in-depth coverage of radar digital signal processing (DSP) fundamentals and applications. It has been updated to include coverage of measurement accuracy and target tracking. Additionally, to make it more useful as a teaching tool, it now includes end-of-chapter problems and a solutions manual. New to this Edition: New chapter on Measurement Accuracy and Target Tracking Two new appendices--Important Digital Signal Processing Facts; Important Probability Density Function and Their Relationships Addition of 20 to 30 problems to ends of chapters Solutions manual

SPIRAL: Code Generation for DSP Transforms

Abstract: Fast changing, increasingly complex, and diverse computing platforms pose central problems in scientific computing: How to achieve, with reasonable effort, portable optimal performance? We present SPIRAL, which considers this problem for the performance-critical domain of linear digital signal processing (DSP) transforms. For a specified transform, SPIRAL automatically generates high-performance code that is tuned to the given platform. SPIRAL formulates the tuning as an optimization problem and exploits the domain-specific mathematical structure of transform algorithms to implement a feedback-driven optimizer. Similar to a human expert, for a specified transform, SPIRAL "intelligently" generates and explores algorithmic and implementation choices to find the best match to the computer's microarchitecture. The "intelligence" is provided by search and learning techniques that exploit the structure of the algorithm and implementation space to guide the exploration and optimization. SPIRAL generates high-performance code for a broad set of DSP transforms, including the discrete Fourier transform, other trigonometric transforms, filter transforms, and discrete wavelet transforms. Experimental results show that the code generated by SPIRAL competes with, and sometimes outperforms, the best available human tuned transform library code.

A DSP-based active disturbance rejection control design for a 1-kW H-bridge DC-DC power converter

Abstract: This paper presents the design and implementation of an advanced digital controller for a 1-kW H-bridge dc-dc power converter. A new control algorithm based on the active disturbance rejection concept is developed to cope with the highly nonlinear dynamics of the converter and the disturbances. An experimental digital control system is used to implement the new control strategy. It consists of a digital control board based on the TMS320C6711 digital signal processor chip, an analogy I/O board, and a complex programmable logic device pulsewidth-modulation generation board. Using a newly developed bandwidth-parametrization technique, an autotuning method based on noise quantification is also developed and tested. Experimental results show the advantages and flexibilities of the new control method for the H-bridge dc-dc power converter.

Digital Signal Processing: Signals, Systems, and Filters

Abstract: PREFACE Chapter 1: Introduction to Digital Signal Processing Chapter 2: The Fourier Series and Fourier Transfer Chapter 3: The z Transform Chapter 4: Discrete-Time Systems Chapter 5: Application of the z Transform Chapter 6: The Sampling Process Chapter 7: The Discrete Fourier Transform Chapter 8: Realization of Digital Filters Chapter 9: Design of Nonrecursive (FIR) Filters Chapter 10: Approximations for Analog Filters Chapter 11: Design of Recursive (IIR) Filters Chapter 12: Recursive (IIR) Filters Satisfying Prescribed Specifications Chapter 13: Random Signals Chapter 14: Effects of Finite Word Length in Digital Filters Chapter 15: Design of Nonrecursive Filters Using Optimization Methods Chapter 16: Design of Recursive Filters Using Optimization Methods Chapter 17: Wave Digital Filters Chapter 18: Digital Signal Processing Applications APPENDIX A: COMPLEX ANALYSIS APPENDIX B: ELLIPTIC FUNCTIONS INDEX

Dirty RF: a new paradigm

Abstract: The implementation challenge for new low-cost low-power wireless modem transceivers has continuously been growing with increased modem performance, bandwidth, and carrier frequency. Up to now we have been designing transceivers in a way that we are able to keep the analog (RF) problem domain widely separated from the digital signal processing design. However, with today's deep sub-micron technology, analog impairments-dirt effects-are reaching a new problem level which requires a paradigm shift in the design of transceivers. Examples of these impairments are phase noise, non-linearities, IQ imbalance, ADC impairments, etc. In the world of dirty RF we assume to design digital signal processing such that we can cope with a new level of impairments, allowing lee-way in the requirements set on future RF sub-systems. This paper gives an overview of the topic and presents analytical evaluations of the performance losses due to RF impairments as well as algorithms that allow to live with imperfect RF by compensating the resulting error effects using digital baseband processing

An ultra-wideband transceiver architecture for low power, low rate, wireless systems

Abstract: This paper presents the system architecture, modeling, and design constraints for a baseband, integrated, CMOS, impulse ultra-wideband transceiver targeting very low power consumption on the order of 1 mW. Intended for a sensor network application, the radio supports low communication rates (/spl sim/100 kpbs) and ranging capabilities over short distances (/spl sim/10 m). Based on a "mostly digital" architecture, the analog complexity is reduced by moving the A/D convertor as close to the antenna as is reasonable. Pulses are generated from simple digital switches, overlaying the signal energy on the lower FCC UWB band (0-960 MHz). Reception is achieved using baseband gain blocks feeding a time-interleaved bank of low resolution A/D converters. A window of energy is captured in time and fed to the digital backend for processing. To save power and area, the digital backend implements only a pulse template correlation filter block overlaid with an additional spreading code. As a pulse template is used, no specific channel estimation or interference cancellation is assumed. The system performance is quantified for this case and implementation tradeoffs are explored with a strong focus on reducing power consumption. In particular, the issues of modulation choice, clock generation, gain and noise figure, ADC resolution, and digital signal processing requirements will be discussed.

Coherent demodulation of 40-Gbit/s polarization-multiplexed QPSK signals with 16-GHz spacing after 200-km transmission

Abstract: 40-Gbit/s polarization-multiplexed QPSK signals with 16-GHz spacing are demodulated after 200-km transmission by using a homodyne phase-diversity receiver. The highlights of our scheme are electrical post-filtering and digital signal processing that enhance the BER performance.

LMS adaptive filters using distributed arithmetic for high throughput

Abstract: We present a new hardware adaptive filter architecture for very high throughput LMS adaptive filters using distributed arithmetic (DA). DA uses bit-serial operations and look-up tables (LUTs) to implement high throughput filters that use only about one cycle per bit of resolution regardless of filter length. However, building adaptive DA filters requires recalculating the LUTs for each adaptation which can negate any performance advantages of DA filtering. By using an auxiliary LUT with special addressing, the efficiency and throughput of DA adaptive filters can be of the same order as fixed DA filters. In this paper, we discuss a new hardware adaptive filter structure for very high throughput LMS adaptive filters. We describe the development of DA adaptive filters and show that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that DA adaptive filters have a potential area and power consumption advantage over digital signal processing microprocessor architectures.

Signal denoising techniques for partial discharge measurements

Abstract: One of the major challenges of on-site partial discharge (PD) measurements is the recovery of PD signals from a noisy environment. The different sources of noise include thermal or resistor noise added by the measuring circuit, and high-frequency sinusoidal signals that electromagnetically couple from radio broadcasts and/or carrier wave communications. Sophisticated methods are required to detect PD signals correctly. Fortunately, advances in analog-to-digital conversion (ADC) technology, and recent developments in digital signal processing (DSP) enable easy extraction of PD signals. This paper deals with the denoising of PD signals caused by corona discharges. Several techniques are investigated and employed on simulated as well as real PD data.

FPGA implementations of fast Fourier transforms for real-time signal and image processing

Abstract: Applications based on the fast Fourier transform (FFT), such as signal and image processing, require high computational power, plus the ability to experiment with algorithms. Reconfigurable hardware devices in the form of field programmable gate arrays (FPGAs) have been proposed as a way of obtaining high performance at an economical price. However, users must program FPGAs at a very low level and have a detailed knowledge of the architecture of the device being used. They do not therefore facilitate easy development of, or experimentation with, signal/image processing algorithms. To try to reconcile the dual requirements of high performance and ease of development, this paper reports on the design and realisation of a high level framework for the implementation of 1-D and 2-D FFTs for real-time applications. A wide range of FFT algorithms, including radix-2, radix-4, split-radix and fast Hartley transform (FHT) have been implemented under a common framework in order to enable the system designers to meet different system requirements. Results show that the parallel implementation of 2-D FFT achieves linear speed-up and real-time performance for large matrix sizes. Finally, an FPGA-based parametrisable environment based on 2-D FFT is presented as a solution for frequency-domain image filtering application.

Monobit digital receivers for ultrawideband communications

Abstract: Ultrawideband systems employ short low-power pulses. Analog receiver designs can accommodate the required bandwidths, but they come at a cost of reduced flexibility. Digital approaches, on the other hand, provide flexibility in receiver signal processing but are limited by analog-to-digital converter (ADC) resolution and power consumption. In this paper, we consider reduced complexity digital receivers, in which the ADC is limited to a single bit per sample. We study three one-bit ADC schemes: 1) fixed reference; 2) stochastic reference; and 3) sigma-delta modulation (SDM). These are compared for two types of receivers based on: 1) matched filtering; and 2) transmitted reference. Bit-error rate (BER) expressions are developed for these systems and compared to full-resolution implementations with negligible quantization error. The analysis includes the impact of quantization noise, filtering, and oversampling. In particular, for an additive white Gaussian noise channel, we show that the SDM scheme with oversampling can achieve the BER performance of a full-resolution digital receiver.

An Evaluation of the Suitability of FPGAs for Embedded Vision Systems

Abstract: Reconfigurable hardware, in the form of Field Programmable Gate Arrays (FPGAs), is becoming increasingly attractive for digital signal processing problems, including image processing and computer vision tasks. The ability to exploit the parallelism often found in these problems, as well as the ability to support different modes of operation on a single hardware substrate, gives these devices a particular advantage over fixed architecture devices such as serial CPUs and DSPs. Further, development times are substantially shorter than dedicated hardware in the form of Application Specific ICs (ASICs), and small changes to a design can be prototyped in a matter of hours. On the other hand, designing with FPGAs still requires expertise beyond that found in many vision labs today. This paper looks at the advantages and disadvantages of FPGA technology, its suitability for image processing and computer vision tasks, and attempts to suggest some directions for the future.

An FPGA-based VLIW processor with custom hardware execution

Abstract: The capability and heterogeneity of new FPGA (Field Programmable Gate Array) devices continues to increase with each new line of devices. Efficiently programming these devices is increasing in difficulty. However, FPGAs continue to be utilized for algorithms traditionally targeted to embedded DSP microprocessors such as signal and image processing applications.This paper presents an architecture that combines VLIW (Very Large Instruction Word) processing with the capability to introduce application specific customized instructions and complex hardware functions. To support this architecture, a compilation and design automation flow are described for programs written in C.Several design tradeoffs for the architecture were examined including number of VLIW functional units and register file size. The architecture was implemented on an Altera Stratix II FPGA. The Stratix II device was selected because it offers a large number of high-speed DSP (digital signal processing) blocks that execute multiply accumulate operations.We show that our combined VLIW with hardware functions exhibit as much as 230X speedup and 63X on average for computational kernels for a set of benchmarks. This allows for an overall speedup of 30X and 12X on average for signal processing benchmarks from the MediaBench.

A high-performance EIT system

Abstract: This paper presents the development of a new electrical impedance tomography system for online measurement of two-phase flows with axial velocities up to 10 ms/sup -1/. The system is designed in a modular fashion and can consist of several data acquisition modules and computing modules. The data acquisition module includes a voltage controlled current source with a direct-current-restoration circuit, an equal-width pulse synthesizer unit and a synchronized digital demodulation unit. A new concept of current switching scheme is developed to enhance the ac coupling speed. The computing module includes a digital signal processor (TMS320C6202/6713) with memory, multichannel buffered serial ports and an IEEE1394 communication interface. Several DSP modules can be pipelined for a series of tasks ranging from measurement control to image reconstruction to flow velocity implementation. The performances have been tested and some trial results are reported. A data acquisition speed of 1164 dual-frames (2.383 million data points) per second has been achieved with a root mean square error less than 0.6% at 80 kHz in static test application. An application in the measurement of vertical oil-in-water pipe flow is reported.

Digital RF processing: toward low-cost reconfigurable radios

Abstract: RF circuits for multi-gigahertz frequencies have recently migrated to state-of-the-art low-cost digital CMOS processes. This article visits fundamental techniques recently developed that migrate RF and analog design complexity to the digital domain for a wireless RF transceiver. All-digital phase locked loop and direct RF sampling techniques allow great flexibility in reconfigurable radio design. Digital signal processing concepts are used to help relieve analog design complexity, allowing one to reduce cost and power consumption in a reconfigurable design environment. Software layers are defined to enable these architectures to develop an efficient software-defined radio. The ideas presented have been used to develop two generations of commercial digital RF processors: a single-chip Bluetooth radio and a single-chip GSM radio.

Introduction to Random Signals and Noise

Abstract: Random signals and noise are present in many engineering systems and networks. Signal processing techniques allow engineers to distinguish between useful signals in audio, video or communication equipment, and interference, which disturbs the desired signal. With a strong mathematical grounding, this text provides a clear introduction to the fundamentals of stochastic processes and their practical applications to random signals and noise. With worked examples, problems, and detailed appendices, Introduction to Random Signals and Noise gives the reader the knowledge to design optimum systems for effectively coping with unwanted signals. Key features: • Considers a wide range of signals and noise, including analogue, discrete-time and bandpass signals in both time and frequency domains. • Analyses the basics of digital signal detection using matched filtering, signal space representation and correlation receiver. • Examines optimal filtering methods and their consequences. • Presents a detailed discussion of the topic of Poisson processed and shot noise.

Interactive online undergraduate laboratories using J-DSP

Abstract: An interactive Web-based simulation tool called Java-DSP (J-DSP) for use in digital signal processing (DSP)-related electrical engineering courses is described. J-DSP is an object-oriented simulation environment that enables students and distance learners to perform online signal processing simulations, visualize Web-based interactive demos, and perform computer laboratories from remote locations. J-DSP is accompanied by a series of hands-on laboratory exercises that complement classroom and textbook content. The laboratories cover several fundamental concepts, including z transforms, digital filter design, spectral analysis, multirate signal processing, and statistical signal processing. Online assessment instruments for the evaluation of the J-DSP software and the associated laboratory exercises have been developed. Pre/postassessment data have been collected and analyzed for each laboratory in an effort to assess the impact of the tool on student learning.

Multi-protocol radio frequency identification transponder tranceiver

Abstract: A transceiver for a RFID reader and a transceiver for a RFID transponder (tag) allow communication between the two devices. The RFID reader utilizes an analog front end and a digital backend. In the receiver portion of the transceiver, the front end of the RFID reader uses a pair of down-conversion mixers to demodulate a received signal into in-phase (I) and quadrature (Q) components and analog-to-digital converters (ADC) digitize the signal. A digital signal processor (DSP) in the back end processes the digital signal and uses a matched filter for data detection. The RFID tag receives an inductively coupled signal from the reader and the receiver portion of the tag uses a pulse/level detector that employs an analog comparator and a sample and hold circuit to detect the received signal. A digital decoder/controller is used to decode the incoming data and to establish a sampling clock for the pulse/level detector. An automatic gain control (AGC) circuit adjusts a receiver gain according to the received signal strength and controls tuning of magnetic coupling circuitry.

Self-calibration of input-match in RF front-end circuitry

Abstract: The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

Implementation of a 50-kW four-phase switched reluctance motor drive system for hybrid electric vehicle

Abstract: A high-performance fully digital controller has been designed for the drive of a 50-kW four-phase switched reluctance (SR) motor built for a hybrid electric vehicle (HEV). The SR machine is specifically designed and manufactured to have high power density and low acoustic noise. The controller is based on the advanced digital signal processor (DSP) with internal CAN interface-TMS320F2406 and complex programmable logic device (CPLD)-EPM7128S. The experimental results show that the controller is met with the system specification and requirement, satisfactorily.

Periodic signal enhancement system

Abstract: A signal enhancement system improves the understandability of speech or other audio signals. The system reinforces selected parts of the signal, may attenuate selected parts of the signal, and may increase SNR. The system includes delay logic, a partitioned adaptive filter, and signal reinforcement logic. The partitioned adaptive filter may track and enhance the fundamental frequency and harmonics in the input signal. The partitioned filter output signals may approximately reproduce the input signal, delayed by an integer multiple of the period of the fundamental frequency of the input signal. The reinforcement logic combines the input signal and the filtered signals to produce an enhanced output signal.

A low-cost, high-performance, digital signal processor-based lock-in amplifier capable of measuring multiple frequency sweeps simultaneously

Abstract: A high-performance digital lock-in amplifier implemented in a low-cost digital signal processor (DSP) board is described. This lock in is capable of measuring simultaneously multiple frequencies that change in time as frequency sweeps (chirps). The used 32‐bit DSP has enough computing power to generate N=3 simultaneous reference signals and accurately measure the N=3 responses, operating as three lock ins connected in parallel to a linear system. The lock in stores the measured values in memory until they are downloaded to the a personal computer (PC). The lock in works in stand-alone mode and can be programmed and configured through the PC serial port. Downsampling and multiple filter stages were used in order to obtain a sharp roll off and a long time constant in the filters. This makes measurements possible in presence of high-noise levels. Before each measurement, the lock in performs an autocalibration that measures the frequency response of analog output and input circuitry in order to compensate fo...

Digital architecture for radio-frequency apparatus and associated methods

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Implementation and performance evaluation of DSP-based control for constant-frequency discontinuous-conduction-mode boost PFC front end

Abstract: A digital signal processor (DSP) implementation of digital control for constant-frequency, discontinuous-conduction-mode boost power-factor-correction converter for universal line-voltage (90-264 V/sub rms/) applications is presented A step-by-step design procedure based on digital redesign technique is also provided The performance evaluation of the proposed DSP control is performed on a 400-W prototype It was shown that the implemented DSP-based control can achieve a power factor higher than 099 in the entire line range

Mixed-scaling-rotation CORDIC (MSR-CORDIC) algorithm and architecture for high-performance vector rotational DSP applications

Abstract: The coordinate rotational digital computer (CORDIC) algorithm is a well-known iterative arithmetic for performing vector rotations in many digital signal processing (DSP) applications. However, the large number of iteration is a major disadvantage of this algorithm for its speed performance. Many researchers have proposed schemes to reduce the number of iterations. Nevertheless, in performing the existing CORDIC algorithms, the norm of the vector is usually enlarged so that extra scaling operations are required to deliver the normalized output. In this paper, we merge the two operation phases (microrotations and scaling phases) and propose a new vector rotational scheme called mixed-scaling-rotation coordinate rotational digital computer (MSR-CORDIC) algorithm. It can eliminate the overhead of the scaling operations that are inevitable in existing CORDIC algorithms; hence, it can significantly reduce the total iteration number so as to improve the speed performance. The proposed MSR-CORDIC can be applied to DSP applications, in which the rotational angles are known in advance [e.g., twiddle factor in fast Fourier transform (FFT) processor designs]. Moreover, most CORDIC algorithms generally suffer from the roundoff noise in the fixed-wordlength implementations. We also propose two schemes to control and reduce the impairment. Our simulation results show that the MSR-CORDIC algorithm can enhance the signal-to-quantization-noise ratio (SQNR) performance by controlling the internal dynamic range. We also investigate the first- and second-order statistical properties, including the mean and variance of the SQNR. Simulation results show that the MSR-CORDIC can enhance SQNR performance of both first- and second-order statistical properties. At the VLSI architecture level, we proposed a generalized MSR-CORDIC engine for the tradeoff between hardware complexity and quantization error performance. It can further reduce the hardware complexity when compared with the newly proposed extend elementary angle set CORDIC algorithm . The MSR-CORDIC scheme has been applied to a variable-length FFT processor design , and results in significant hardware reduction in implementing the twiddle factor operations.

Method and apparatus for obtaining complete speech signals for speech recognition applications

Abstract: The present invention relates to a method and apparatus for obtaining complete speech signals for speech recognition applications. In one embodiment, the method continuously records an audio stream comprising a sequence of frames to a circular buffer. When a user command to commence or terminate speech recognition is received, the method obtains a number of frames of the audio stream occurring before or after the user command in order to identify an augmented audio signal for speech recognition processing. In further embodiments, the method analyzes the augmented audio signal in order to locate starting and ending speech endpoints that bound at least a portion of speech to be processed for recognition. At least one of the speech endpoints is located using a Hidden Markov Model.

Digital Video Image Quality and Perceptual Coding (Signal Processing and Communications)

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A novel time-domain current-detection algorithm for shunt active power filters

Abstract: A novel current-detection algorithm based on the time-domain approach for three-phase shunt active power filters (APFs) to eliminate harmonics, and/or correct power factor, and/or balance asymmetrical loads is analyzed in this paper. A basic overview and evaluation of the performance of existing current-detection algorithms for active power filters are presented. According to different complicated power quality issues and various compensation purposes, a novel current-detection algorithm is then proposed. Comparing with existing algorithms, this algorithm has shorter response time delay and clearer physical meaning. Different compensating current references can, thus, be accurately and easily obtained by adopting the proposed algorithm. It ensures that the shunt APF can very well achieve different compensation purposes. Moreover, it is very easy to implement this algorithm in a digital signal processor (DSP). Simulation results obtained with MATLAB and testing results on an experimental shunt APF are presented to validate the proposed algorithm.

Unrepeatered optical transmission of 20 Gbit/s quadrature phase-shift keying signals over 210 km using homodyne phase-diversity receiver and digital signal processing

Abstract: Unrepeatered optical transmission of 20 Gbit/s quadrature phase-shift keying (QPSK) signals over 210 km, using a homodyne phase-diversity receiver followed by carrier-phase estimation through digital signal processing is demonstrated. The advantage of the coherent detection with phase estimation leads to significant improvement of the receiver sensitivity compared with differential demodulation. It also enables the observation of the distortion of the complex amplitude due to fibre nonlinearity, offering new tools to monitor the transmission quality.