Showing papers on "Division (mathematics) published in 1974"

The Parallel Evaluation of General Arithmetic Expressions

Abstract: It is shown that arithmetic expressions with n ≥ 1 variables and constants; operations of addition, multiplication, and division; and any depth of parenthesis nesting can be evaluated in time 4 log2n + 10(n - 1)/p using p ≥ 1 processors which can independently perform arithmetic operations in unit time. This bound is within a constant factor of the best possible. A sharper result is given for expressions without the division operation, and the question of numerical stability is discussed.

Quantal Behavior of a Diffusible Factor Which Initiates Septum Formation at Potential Division Sites in Escherichia coli

Abstract: Analysis of nucleated cell size in a minicell-producing strain of Escherichia coli and in its parental strain shows that the two distributions are considerably different. A model is proposed to account for this difference. The model states that: (i) in the mutant population, the cell poles are available as potential division sites in addition to the normally located division sites; (ii) the probability of a division occurring at any of the potential division sites is equal; and (iii) only enough “division factor” arises at each unit cell doubling to permit a single division. This factor is utilized entirely in the formation of a single septum. Thus, the occurrence of a polar division with the production of an anucleate minicell (which occurs only in the mutant strain) prevents the occurrence of a non-polar division, with the result that the average nucleated cell length is increased in minicell-producing strains. The model has been used to construct a theoretical population, and a number of parameters of the real and theoretical populations have been compared. The two populations are very similar in all of the parameters measured.

A Generalized Pipeline Array

Abstract: A generalized pipeline cellular array has been proposed which can perform all the basic operations such as multiplication, division, squaring, and square rooting. The different modes of operation are controlled by a single control line. An expression for time delay has been obtained. Further, it has been shown that these arithmetic operations can be overlapped in the pipe in any desired sequence, and thus significant speed improvement can be achieved. The array is fully iterative and hence is suitable for large-scale integration (LSI).

The inverse of the generalized vandermonde matrix through the partial fraction expansion

Abstract: A simple method for finding the inverse Vandermonde matrix is presented. The technique involves determination of the partial fraction expansion of rational functions. Only synthetic division and longhand division are required, which make the process very suitable for hand calculation. Alternatively, simple recurrent relations are also developed for computer use.

Multiple purpose electronic counting system

Abstract: An electronic counting system with a solid state chip circuit having a multiple purpose counting and control system with an input signal operated control circuit selectively operable by input control signals from external circuitry for providing multiplication, division and rate computation functions and counting and two-stage predetermining functions, and also selectively operable by input control signals for selectively operationally partitioning a BCD RAM of the chip circuit into two separate RAM sections having selected numbers of BCD decade sets and operable to provide independent functions or interrelated functions. Data may be entered into each BCD decade of each of two BCD decade registers of the RAM directly by BCD and entry select signals applied to the chip circuit or by push button and entry select signals applied to the chip circuit.

Time division multiple transmission control apparatus

Abstract: A time division multiple transmission control apparatus which comprises a central processing device for generating a reference timing signal having a predetermined frequency and a time division multiple signal having substantially the same frequency for controlling a plurality of electrical devices during predetermined time periods, terminal processing devices for controlling each electrical device during a different predetermined time period under the control of said reference timing signal and said time division multiple signal and means for generating a phase difference between said reference timing signal and said time division multiple signal.

Arrangement for preventing interruptions in a time division multiplex transmission link for transfer of data

Abstract: The present invention relates to an arrangement in a time division multiplex link having at least two pairs of multiplexors and demultiplexors interconnected by separate transmission lines, i.e., redundant transmission systems, with delay, in which time division multiplex channels are formed through the cyclic scanning of the multiplexor inlets and demultiplexor outlets, respectively so that data signals presented to the multiplexor inlets are transferred via the time division multiplex channels in the form of sampling signals to regeneration arrangements connected to the demultiplexor outlets. The sampling signals passed over the separated (redundant) time division multiplex channels are interlaced, i.e., different delays on different transmission lines, thereby producing a resultant sampling density which, when a fault occurs, is reduced by a factor corresponding to the share of the faulty channel in the total number of channels.

Time-space-time division switching network

Abstract: In a large time-space-time division switching network, particularly one employing a multistage space-division switch, one time-division elementary time is too brief to enable transmission of addresses of crosspoints to be completed through all the stages of the multistage switch, and also provide for transmission of the speech sample. To cope with this situation, two successive network elementary times are used, each elementary time being divied into two half-times, i.e., a first half-time and a second half-time. First half-times are used for transmitting addresses of crosspoints to be closed immediately. Second half-times are used for storing data concerning further crosspoint addresses plus a speech sample. Addresses are propagated through a speech sample path according to a "staggered operation", thereby reducing the requirements for memory dedicated to crosspoint addresses.

Possibility of construction of an arithmetic unit based on controlled optical transparencies

Abstract: An analysis is made of the possibility of construction of arithmetic units based on the passage of light signals through electric-field-controlled optical transparencies. Such arithmetic units can perform any Boolean algebraic operations. Methods for performing the basic arithmetic operations (addition, subtraction, multiplication, and division) are described. A brief discussion is given of the block diagram of an optoelectronic arithmetic unit with a speed of several tens of millions of algorithmic operations per second.

Long Division: An Example of Dynamic Programming

Abstract: The familiar method of long division provides an excellent example of dynamic programming. A five-step division problem is solved by both methods. The five steps make up a five-stage dynamic program. The first step involves selecting a trial divisor, a decision, which minimizes the remainder after even division. This remainder is the state carried over to the next stage. Division proceeds recursively until the final stage is reached. Thus as is typical of the dynamic programming technique, one problem in five unknowns (the five-digit quotient) replaces the original problem by five simpler problems each of one unknown.

Calculating extreme surface temperatures

Abstract: Professor Hoglund, of the Division of Building Technology, Royal Institute of Technology, Stockholm, submits a theoretical method of calculating extreme temperatures on the outer surfaces of buildings under non-stationary conditions, taking into account both heat tansfer by convection and exchange of short-wave and long-wave radiation with the surroundings.

A Low-Cost Binary Division Circuit for Digital Instrumentation

Abstract: A simple low-cost "latched" division network is described which is capable of executing the "division by time" operation commonly required in many digital instrumentation applications. Typical of these are velocity and acceleration measurements. The division network which was implemented and is described here is capable of performing division with two 16-b numbers (1 b being the sign bit) and producing a 15-b answer within 4.0 ?s (worst case delay). It uses a modified version of the restoring division technique and assumes positive numbers as input, although the modification to operate with negative numbers is possible. A comparison of this technique is made with a previously published design used in a tachometer. Results indicate that significant improvement is possible in both speed and hardware.

A Time-Division Data Switch

Abstract: Modern carrier systems have evolved in which all transmission is digital and channels are obtained by time-division multiplexing. A time-division switch, which, as a consequence of this environment is very simply configured, is presented. Random access memories and shift registers are employed in a configuration which differs from the time division switch canonical form. In this switch both space and time transfers are performed simultaneously in an identical manner. The structure allows short setup time with high call setup capacity, yet the hardware implementation is simple and highly regular.

Computation device and method

Abstract: A computation device for performing the mathematical operations of multiplication and division is disclosed. The device has a housing in which an indicator is fixedly located. There is a first logarithmic scale mounted in the housing so as to be movable with respect to the indicator. A second logarithmic scale is mounted so as to be movable adjacent the first scale and a gearing arrangement is provided which is engageable with the first and second scales for fixing the positions of the scales with respect to each other and for jointly moving the scale with respect to the indicator. The computation device can be used for converting a value in one set of units directly into a value in another set of units by providing a third logarithmic scale movable in fixed relation with the first scale. A method of converting from a value in one set of units to a value in another set of units using the computation device according to the invention is also disclosed.

Comments on "An Augmented Iterative Array for High Speed Division"

Abstract: Division is a serial operation and it is argued that parallel division arrays are unnecessary since serial circulating dividers can be designed which are almost as fast, when using the same technology, but are a fraction of the cost.

Divide-and-Correct Algorithm for Division in a Negative Base

Abstract: A divide-and-correct algorithm is described for multiple-precision division in the negative base number system. In this algorithm an initial quotient estimate is obtained from suitable segmented operands; this is then corrected by simple rules to arrive at the true quotient.