Showing papers on "Division (mathematics) published in 1979"

Optimum Detection of Code Division Multiplexed Signals

Abstract: The concept of FM-CW Doppler processing is explained by showing it to be a special case of a correlation receiver with a frequency offset reference. For a linear FM signal, time delay and frequency shift can be arranged to cancel each other, and this results in conManuscript received April 14, 1978, revised August 4, 1978. This work was partially supported by Air Force Project Order Y77-847, \"IM-CW Doppler Radar Wind Shear Detector.\" U.S. Government work, not protected by U.S. copyright. v RS(r) = s(t) s(t --T )I

Control information communication arrangement for a time division switching system

Abstract: A time division switching system having distributed control processors is disclosed. The distributed processors exchange control messages and cooperate in the completion of talking paths between subscribers. Each control message includes an address portion defining the destination for the control message and is transmitted to a time-shared space division switch on the same time multiplex lines that speech representations are transmitted. Control messages are routed by the time-shared space division switch to a control distribution unit where the address portion is interpreted. When the address portion defines a distributed processor which controls the time-shared space division switch, the control distribution unit transmits the associated control message directly to that processor. Alternatively, when the address portion defines one of the other distributed processors the control distribution unit transmits the associated control message to the defined processor via the time-shared space division switch.

High-Speed Arithmetic Arrays

Abstract: High-speed multifunction arithmetic arrays for multiplication, division, square and square-root operations are presented in this paper. These arrays seem attractive due to their versatility and speed. A recently described quotient-bit evaluation technique that uses the carry-save method in a nonuniform division array is extended here for the restoring-division process. This array includes the multiplication process as well, and the division time approaches that of multiplication. The design objective of multifunctional arithmetic arrays precludes consideration of other high-speed division techniques. A further extension of the restoring division process is shown to make the design of an array for square/square-root operation straightforward. The two underlying arrays can be coalesced to perform any one of the four operations. Possible methods of merging the arrays, with their relative merits, are also discussed. For illustration purposes, complete internal details of such a generalized pipelined array for 4-bit operation is included in this paper. Due consideration is also given to the possibility of large-scale integration of the different arrays illustrated in this paper.

Manufacture of semiconductor device

Abstract: PURPOSE:To avoid occurrence of the distortion on the PN junction surface by giving the pressure division with the division groove provided so that it may not reach the PN junction from the surface of one side when the PN junction is formed on the semiconductor substrate and then the substrate is divided with the division groove provided. CONSTITUTION:P-type layer 12 is epitaxial-grown on N-type GaP substrate 11, and then division groove 15 is provided via dicing so that it may not reach PN junction 13 caused from the back side of large-thickness substrate 11. Then the pressure is applied from the side of layer 12 on the other surface to form split 16 toward the area where no groove 15 is formed, thus obtaining a number of light emitting elements 17 of a fixed size. In such way, no distortion is caused on PN junction surface 13 with no deterioration of the light emitting output. This method can also be applied effectively to the division of other semiconductor elements in addition to the light emitting element.

Development of a Time-Division Switching Network Usable in a Very Large Range of Capacities

Abstract: Well adapted to medium size systems, the T switching networks fully proved the operational value of the time division principles. For higher capacities, the more usual realizations are now STS and mainly TST networks. These are attractive as the growth of the equipment proportional to the square of the number of subscribers is limited to the intermediate stage (or stages). Drastic improvements in semiconductor technology, particularly in the memory field, allow another step: mixing in the same I.C. can, the T and S stages. In this concept, staggering or even functional discrimination of T and S appears to be useless and artificial. The resulting matrix circuit has quite symmetrical input-outputs and the multiple incoming bit positions are distributed to the output in whatever time and space arrangement that is needed. This paper describes the networks based on this concept.

Continuity verification arrangement

Abstract: A time division switching system having distributed control processors is disclosed. The switching system includes time-slot interchange units having associated subscriber sets and a time-shared space division network for interconnecting the time-slot interchange units. Each of the time-slot interchange units and the time-shared space division network are controlled by separate control processors. In response to called subscriber set identifying information from a calling subscriber set, the control processor associated with the time-shared space division network completes the communication path through the time-shared space division network to connect the time-slot interchange units associated with the calling and called subscriber sets. The control processors in the time-slot interchange units then determine if communication path continuity is present between them before the subscriber sets are connected to the communication path through the time-slot interchange units. Additionally, arrangements are included for detecting loss of continuity in the communication path.

Division is good

Abstract: We study the power of RAM acceptors with several instruction sets. We exhibit several instances where the availability of the division operator increases the power of the acceptors. We also show that in certain situations parallelism and stochastic features ('distributed random choices') are provably more powerful than either parallelism or randomness alone. We relate the class of probabilistic Turing machine computations to random access machines with multiplication (but without boolean vector operations). Again, the availability of integer division seems to play a crucial role in these results.

Division processing method system having 2N-bit precision

Abstract: A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q 1 +Q 2 ×2-n (Q 1 , Q 2 : binary numbers). The binary numbers Q 1 and Q 2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q 1 is used as a part of the data for performing the division processing of Q 2 , thus effectively transferring any error evolving during the processing of Q 1 to Q 2 . The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

Time division switching circuit with time slot interchange

Abstract: A time division switching circuit with time slot interchange uses an input shift register to convert one-frame binary coded input data of time division multiplex type from an incoming line into a parallel bit output. The parallel bit output undergoes gate control of a gate matrix and its bit array is statically changed to a given bit array. The on/off control of the gate at the cross point of the gate matrix is conducted according to parallel bit outputs of a plurality of control shift registers which stores predetermined contents. The one-frame bit data thus exchanged are supplied to an output shift register. They are transmitted to an outgoing line as binary coded output data of time division multiplex type.

Transfer bar divider

Abstract: PURPOSE:For reducing dividing time, to enable, of the three divisions of a transfer bar, a one end side one to transfer oppositely to the transfer direction of the other end side one transferred by a feed carrier. CONSTITUTION:A transfer bar 7 is divided in 7L, 7C and 7R. When a die is replaced, said divisions 7L, 7C are 7R are separated, and said central division 7C is replaced together with said die. For this purpose, said bar 7 and a bolster 5 are let down and up respectively, and said central division 7C is placed to be supported on the supporter 16 thereof. Separation and connection mechanisms 81 and 82 are separated. A pin 75 is protruded to engage the projection of said division 7L by means of a cylinder mechanism and said division 7L is transferred leftward by handling a cylinder 79. At the same time, said division 7R is transferred rightward by transferring a feed carrier 14 in the same direction. Thus, control can be made easily since said separation and connection mechanmisms 81 and 82 can be operated at a time.

Watt and var transducer

Abstract: A watt and var transducer which alternately generates each function in response to commonly shared time division multiplication circuitry, and which provides a continuous indication of watt and vars via separate filtering and amplifier output stages.

Teaching Division of Fractions with Understanding.

Abstract: cular regions which are cut from colored construction paper and have the fraction names written on one side only. All fraction sections of the same size should be of the same color. They are easily made by drawing the fraction sections on duplicating masters and feeding construction paper through the duplicating machine just as you would ordinary duplicating paper. The fraction sections that I will refer to are

Arbitrary precision arithmetic in Algol 68

Abstract: Algol 68 enables facilities for such things as arbitrary precision arithmetic to be provided in a particularly elegant and convenient way. The library segment mlaritha which provides such facilities is described. This segment enables numerical quantities to be stored and manipulated with almost the same degree of ease, or difficulty, as REAL quantities but with arbitrary and dynamically variable precision. The method of ‘NUMBER’ storage used in mlaritha is discussed in detail and the fundamental algorithms used for the arithmetic operations of addition, multiplication and division, etc., are described. Special attention is given to the ‘costs’ inherent in the use of the system; particularly in the time ‘costs’ of each of the operations and the dependence on precision.

Time division switching network

Abstract: A switching system for telephone exchanges employing pulse code modulation (PCM). The time division switching network uses standard circuits of a single type, i.e., symmetrical time division matrices (MTS) and, in a particular embodiment, one PCM telephone junction is multipled onto two inputs of two MTSs and the latter are rejoined by two bi-directional junctions so that the construction of telephone exchange according to the invention permits simple and easy extensions of the capacity of the switching system.

Power divider with randomly varying incremental power transfer

Abstract: By randomly varying the difference in the phase constants and/or the coupling coefficient along the lengths of two or more wavepaths, an equal division power divider is obtained whose operation is not critically dependent upon its dimensions.

Division multiple system for frequency deviation keying frequency

Abstract: PURPOSE:To facilitate an easy time-division use as well as to realize a small size for the device, by multiplying the signal obtained through the bend limitation by the sum of the carrier waves of the mark and space paths to obtain the sum and at the same time eliminating the unnecessary wave.

Graphic printer device

Abstract: PURPOSE:To reduce the capacity of vector memory by reducing the frequencies of the reproducing action when the full screen is scanned and converted at one time, and also to shorten the recording time by reducing the reading and writing time of the vector memory. CONSTITUTION:Screen region 1 to be recorded is divided into partial regions 11-14. And for instance, vectors c-g exist at partial region 12. As vector data c, d and g belong to other partial regions, these data are stored in all corresponding memory regions. After this, region 12 is drawn out to the partial vector memory to perform divisions 121-125 through designations of the upper and lower limit counters at the divided part, and distrubution pulses are generated sequentially based on the divided vector information to be memorized in one of the memory units which are switched circularly in correspondence to the division. The information is then read out to be used as the scanning pattern signal, and this action is repeated to obtain the scanning pattern signal for the full screen.

Multiplication and efficiency conversion*connection device for timee division channel system

Abstract: PURPOSE:To secure an economical conversion for the multiplication number and the efficiency at the junctions between time-division multiple circuits to each other by combining the holding circuit and the holding timing, and thus to enhance the flexibility for the mutual connection of each multiplying system between the time-division transmission line and the channel.