Showing papers on "Division (mathematics) published in 1986"

Log depth circuits for division and related problems

Abstract: We present optimal depth Boolean circuits (depth $O(\log n)$) for integer division, powering, and multiple products. We also show that these three problems are of equivalent uniform depth and space complexity. In addition, we describe an algorithm for testing divisibility that is optimal for both depth and space.

Data processing system

Abstract: A data processing system having an arithmetic unit is designed for a multiplication of n-place numbers in 2's complement according to the Booth algorithm, and for division of unsigned numerals. A 2n-stage shift register is connected over a logical control circuit to the operation code inputs of an ALU. The control circuit automatically forms instruction code signals to the ALU as a function of informational bits derived from the shift register, whereas other operation code input signals are directly connected to the operation code inputs. The control circuit is a sequential circuit having a multiplexer for the selective through-connection of the multiplication code signals, the division code signals, or other operation code signals to the operation code inputs of the ALU.

Hand-held copying apparatus

Abstract: A hand-held copying apparatus has a reading window of a read division disposed on a leading end outwardly of two parallel rollers which define a reference plane placed on the surface to be read. A storage division for storing information read by the read division is provided integrally with the read division, and information stored in the storage division is recorded through a recording head which is moved relatively along a recording paper at a speed corresponding to the moving speed of the apparatus detected by a movement encoder mechanism.

Blurring preventive camera

Abstract: PURPOSE: To inform a photographer of the presence/absence of blurring in the course of photographing so that he can take a faultless photograph, by comparing a blurring value with a reference blurring value at which blurring is allowable and actuating a warning means when the blurring value is larger than the reference value. CONSTITUTION: Data stored and held in a blurring quantity storing circuit 52 while a shutter is run are outputted to a blurring quantity dividing circuit 53 and blurring quantities while the shutter is run are divided in time series. Then a blurring value (e) which is calculated from the difference between the maximum and minimum values of the blurring quantities after the division by the circuit 53 is compared with a reference blurring value (b) at a blurring quantity comparing/discriminating circuit 54. When the blurring value (e) is larger, it is outputted to an alarm display driving circuit 56 and a display 57 is caused to display an alarm so that the photographer can know that the photograph he has just taken is blurring and he can be urged to take the photograph again. COPYRIGHT: (C)1988,JPO&Japio

A simple division method for solving Diophantine equations and associated problems

Abstract: Based on the transfer function matrices or the matrix fraction descriptions of multivariable systems, a simple division method in conjunction with the method owing to Wolovich and Antsaklis (1984) is presented in this paper for obtaining the observability and controllability indices, the irreducible right (left) matrix fraction descriptions from reducible or irreducible left (right) matrix fraction descriptions, the greatest common divisors of two polynomial matrices and the solution of a Diophantine equation, without utilizing the state-space realization of the matrix Traction description.

General division in the symmetric residue number system

Abstract: In the residue number system, the arithmetic operations of addition, subtraction, and multiplication are executed in the same period of time without the need for interpositional carry. There is a hope for high-speed operation if residue arithmetic is used for digital computation. The division process, which is one of the difficulties of this operation, is developed in the symmetric residue number system. The method described here is iterative in nature and requires the availability of two tables of the symmetric residue representations of a certain kind of integer. An algorithm for general division is derived, and the way of choosing the entries which are used to find a quotient is discussed.

Symplectic modules

Abstract: A symplectic module is a finite group with a regular antisymmetric form. The paper determines sufficient conditions for the invariants of the maximal isotropic subgroups (Lagrangians), and asymptotic values for a lower bound of a group which contains Lagrangians of all symplectic modules of a fixed orderpn. These results have application to the splitting fields of universal division algebras.

Linear system reduction by the modified factor division method

Abstract: A novel method of linear system simplification is presented based on a modified factor division approach. It is seen to be more flexible than most model reduction methods in that families of reduced models may be easily generated by varying a single parameter in the modified transfer function denominator. It also guarantees stable reduced models of stable systems and preserves initial time moments and Markov parameters of the system. An example illustrates its application.

Generating wireframes from set-theoretic solid models by spatial division

Abstract: Wireframe modelling has been discredited as a primary shape representation technique, but is still useful as a fast way to display simple objects, in particular when selecting projections. Computing wireframes from set-theoretic solid models is potentially very time-consuming. Recursive division of the object space may easily be used to accelerate this process, but the resulting wireframes are unnecessarily segmented. By searching for the vertices of a model and deriving submodels, which are then used to find edges between vertices, a program has been written that both exhibits the good complexity performance of recursive division and produces wireframes containing maximal length wires.

SRT division diagrams and their usage in designing intergrated circuits for division

Abstract: This paper describes the construction and analysis of several diagrams which depict SRT division algorithms. These diagrams yield insight into the operation of the algorithms and the many implementation tradeoffs available in custom circuit design. Examples of simple low radix diagrams are shown, as well as tables for higher radices. The tables were generated by a program which can create and verify the diagrams for different division schemes. Also discussed is a custom CMOS integrated circuit designed which performs SRT division using self-timed circuit techniques. This chip implements an intermediate approach between a fully combinational array and a fully iterative in time method in order to get both speed and small silicon area.

Saving cycles in floating point division

Abstract: In dividing a pair of binary coded, hexidecimal floating point numbers, leading zero quotient bits are eliminated by comparing the magnitudes of the most significant digits of the fractional parts of the dividend and divisor after the dividend and divisor have been normalized

Pipelined vector divide apparatus

Abstract: In a vector divide apparatus having one or few multipliers, a division between two vectors each comprising a plurality of vector elements is performed. A predetermined number of partial quotients are repetitively calculated for each division between vector elements by using the multiplier. In order not to overlap the division operation between consecutive vector elements during calculation of partial quotients using the multiplier, the period of starting the division between vector elements is shortened whereby the vector divide apparatus can be pipelined.

Method and apparatus for numerical division

Abstract: The invention provides a method and apparatus for radix-p non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-p quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-p digit of each of these partial remainders, the process generates a radix-β quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating succesively generated quotient digits to produce a final quotient value.

Swim through safety division line for pools

Abstract: A swim through safety division line for pools at the slope break between shallow and deep water is disclosed. The division line includes a floating frame held vertically by ballast and having top and bottom bars sufficiently above and below the water surface of the pool to allow swimmers to pass through the frame of the division line without being obstructed as when swimming laps in a pool.

Time division wavelength division and incorporation type optical exchange speech path equipment

Abstract: PURPOSE:To improve economical exchange function on multiplexing optical signals by dividing optical signals corresponding to wavelength and exchanging by an optical time switch spatially and timewise, so that either one of wavelength outputted from the optical time switch is applied to a wavelength converter at every time slot, and converted to the optical signals of wafelength inherent to the wavelength converter, and multiplexed by a multiplexer and sent out to an output highway as a time division wavelength division multiplexing signal. CONSTITUTION:Time division wavelength division multiplexed optical signals are divided by a demultiplexer 1 and spatial connection switching and the exchange of time slot is made by an optical time switch 2, and then multiplexed by a multiplexer 5 and converted to the optical signals of wavelength proper to a wavelength converter 4, multiplexed by a multiplexer 5 and outputted to an output highway as time division wavelength division multiplexing optical signals. As the wavelength converter outputs the optical signals of proper wavelength, constitution and control become simple remarkably compared with devices that outputs the optical signals of various wavelength by switching to correspond to time slot.

Processing information generating system for free curved surface

Abstract: PURPOSE: To generate necessary tool path data at a high speed by being provided with an accuracy determining device to determine the number of the picture element division in a prescribed size accuracy for the difference between a free curved surface and an off-setting polyhedron and a surface roughness determining device to determine a tool feeding width based on a surface coarseness instruction. CONSTITUTION: An accuracy determining preprocessor 21, based on a tolerance designated to an object work, divides the geometrical curved surface generated at a CAD step into many quadrangles and triangles and determines a division accuracy. By the polyhedron division, the model made approximate within the tolerance is generated. Next, a surface roughness determining preprocessor 22 determines the feeding width of a tool based on the designated surface coarseness. The data of the dividing accuracy of an off-setting polyhedron obtained by these preprocessors 21 and 22 and the tool feeding pitch are conveyed to a tool path generating processor composed of a processor 23 for rough cutting and a processor 24 for finishing cut, the curved surface data of the geometrical model are successively processed on these and tool path data are formed. COPYRIGHT: (C)1988,JPO&Japio

Method and apparatus for performing division

Abstract: A method and apparatus for performing division which calculates a quotient from a dividend and a divisor by using recursive subtraction operations without using carry propagation for each subtraction operation. The apparatus contains a circuit (16) for generating a plurality of quotient digits from the divisor and the dividend. The apparatus also contains a circuit (18, 20) for generating the quotient from the quotient digits.

Paper accommodating device

Abstract: PURPOSE: To permit the processing devices such as sorter to be installed, by permitting a division accommodation block consisting of a shift block to be separated by a nearly vertical plane for a transport reversal block. CONSTITUTION: The captioned device is equipped with a transport reversal block 100 for selectively reversing a paper sheet discharged from a printer and a division accommodation block 200 which can be separated by a plane nearly perpendicular to the transport reversal block 100, and the accommodation block 200 is constituted by a shift block 300 for shifting at least the accommodation part on a horizontal plane. Therefore, the discharged paper sheet is reversed upwardly or downwardly by the transport reversal block 100, and accommodated into the division accommodation block 200, and accommodation in each prescribed number of sheets is permitted by the operation of the division accommodation block 300. Other processing devices such as sorter can be installed onto the nearly vertical surface of the transport reversal block 100 from which the division accommodation block 300 is separated, and also the division accommodation block 200 cam be directly installed, and the utilization range can be increased largely. COPYRIGHT: (C)1987,JPO&Japio

An integer based hierarchical representation for VLSI

Abstract: Geometries with 45° line segments are often used in integrated circuit layouts, since they can save considerable area. In the limit, the introduction of 45° lines is only 5% less dense than optimal geometry, i.e. circular geometry, whereas manhattan geometry is 27% less dense [7]. Obviously any actual design cannot make use of this density factor everywhere - but figure 1 illustrates a simple but common routing problem where the introduction of 45° wires substantially reduces the area. There has been a trend towards strict manhattan geometries in recent years, however, since it is commonly believed that design rule checking is complicated by the inclusion of intermediate angles [11, 1, 3, 6]. This paper describes a hierarchical representation that supports a complete circuit description, but restricts the set of allowable lines to be horizontal, vertical and 45°. Points are constrained to lie on an integer grid. Rather than use arbitrary polygons, transistors and connection wires are constructed from paths whose sides and ends are created from an octagonal circle approximation. The geometry for contacts is octagonal and is generated from the same circle approximation. The integer grid and restricted line styles allow the simplification of all the Geometrical Design Rule (GDR) checking algorithms - for example a square root is not required in the point-point distance calculations, and division is never required. In fact this approach requires less computation than typical manhattan systems. All of the calculations that normally require real number representation are expressed in integers, eliminating any possibility of round-off errors.

Digital divider with integer and fractional division capability

Abstract: A digital divider with both integral and fractional division capabilities is provided by utilization of a counter and one decoder to trigger phase reversal and a second decoder to trigger short-cycling of the counter. The first decoder provides phase reversal to cause extra half pulses during the period established by the second decoder to thus create the fractional count needed for fractional division. A control input is included to select either whole number division or fractional division.

Modular lattices and Hermitean forms

Abstract: We give some application of the lattice method in the theory of infinite dimensional quadratic spaces over arbitrary division rings.

Polynomial division circuit on expanded galois field

Abstract: PURPOSE: To attain stable processing independently of the hardware and to improve the processing speed by using the hardware so as to execute the division on the expanded galois field. CONSTITUTION: A stage number smaller than number of terms of a division polynomial g(x) by one of multiplication processing units U 0 ∼U e-1 are connected in cascade, and an EOR circuit E and m-set of delay latches R applying a delay of a unit time corresponding to the transmission period of one word are provided in response to the input vector of m-bit comprising the word of respective terms of an input polynomial f(x), respectively. The multiplication processing unit is equipped with a multiplication coefficient device KA and a vector being the result of multiplication of a coefficient (g) of a term corresponding to the division polynomial g(x) with an m-bit vector of an output polynomial Q(x) outputted from the division processing unit U e is given to EOR circuits E 1 ∼E m , where exclusive OR is applied to each bit. The division processing unit U e is provided with a division coefficient device K v dividing the output vector of the output of the multiplication processing U e-1 by the coefficient of the term of the highest order of the division polynomial g(x) and outputs sequentially the output of the division coefficient device as a quotient polynomial. COPYRIGHT: (C)1988,JPO&Japio