Showing papers on "Division (mathematics) published in 1989"

Efficient bit-serial multiplication and the discrete-time Wiener-Hopf equation over finite fields

Abstract: Discrete-time Wiener-Hopf equations (DTWHEs) over finite fields are considered. It is shown that solving the DTWHE is equivalent to performing division over finite fields. The proof provides a new interpretation of the relationship between bit-serial multiplication and DTWHEs. The interpretation enables bit-serial multiplication over GF(2/sup m/) to be understood more easily. As an example, bit-serial multiplication methods for multiplying any two elements that can be done without performing any transformation, or with only a simple transformation of the bases, are presented. >

Algorithm for high speed shared radix 8 division and radix 8 square root

Abstract: An algorithm for performing radix-8 division and square root in a shared hardware is described. To achieve short iteration cycle time, it utilizes an optimized 'next quotient/root prediction PLA' generally used in a radix-4 SRT division with minimal redundancy. In addition, the partial remainder, partial radicand, quotient, and root are generated and saved in redundant forms, thereby eliminating the slow-carry look-ahead adder from the critical path timing of the iteration cycle. This method successfully avoids the need to generate nontrivial divisor/root multiples (3x, 5x, etc.) and also avoids the complex radix-8 next quotient prediction PLA typically used in a conventional radix-8 SRT division. It also shows that a significant amount of hardware sharing can be achieved when square root and division are performed at the same radix. >

Optical Multiplication And Division Using Modified-Signed-Digit Symbolic Substitution

Abstract: The modified-signed-digit (MSD) number system offers parallel addition and subtraction of any two numbers, with carry propagation constrained only between two adjacent digits. Based on MSD addition, parallel algorithms for multiplication and division are developed in this paper. The optical implementations of these MSD arithmetic algorithms are developed on the basis of symbolic substitution (SS). The space-invariant nature of SS matches well with the parallel nature of the MSD arithmetic algorithms presented. The potential advantages of using these algorithms for optical computing include the significant increase in speed, full exploitation of parallelism, and higher system throughput compared with existing electronic arithmetic processors. The performance of the proposed optical arithmetic system is analyzed and compared with that of state-of-the-art electronic counterparts.

Children's Performance on Multiplicative Word Problems: Elements of a Descriptive Theory

Abstract: Three hundred seventy-seven subjects in six age groups, ranging from 10 to 20 years, were asked to identify the appropriate operation for 24 multiplication and division problems involving price, speed, and measure conversion. For multiplication problems, difficulty was strongly dependent on the type of number in the preferred-multiplier role. Important differences from the general tendency were noted in those change-of-size and mixture problems in which both quantities were measured in the same units. Choice of operation also was affected by the misconception that multiplication makes bigger and division smaller. In division problems, choice was dominated by the numerical preference for dividing by an integer or the smaller of the two numbers; decimal points were sometimes ignored in determining this preference. MMBDS also operated, but not in all problems. In a second experiment with 42 fifteen-yearold students, half were asked to estimate answers and half to choose the correct operation for change-of-size and mixture problems. Estimating the outcome was easier than both choosing the operation for division, and multiplication by numbers less than 1. For multiplication by numbers substantially greater than 1, choosing the operation was easier.

A photonic switch architecture utilizing code and wavelength multiplexing

Abstract: An optical multiplexer and demultiplexer using combined code division and wavelength division multiplexing. The multiplexer comprises a plurality of code division multiplexers, each responsive to a plurality of input signals and a plurality of orthogonal code sequences, and a wave division multiplexer for generating an output signal representing the signals of each code division multiplexer carried on a different wavelength. Each code division multiplexer comprises a plurality of lithium niobate phase shifters, each comprising an indiffused titanium wave guide and a pair of electrodes for the accepting one of the orthogonal code sequences, to module the lightwave being passed through the wave guide. The demultiplexer for extracting a selected input signal, comprises a wavelength selector for selecting the wavelength carrying the selected input signal, a phase shifter for modulating the selected wavelength signal by the code sequence of the selected individual input signal, and a PIN photodiode for combining the multiplexed signal with the output of the phase shifter to extract the selected input signal. Advantageously, many signals can be multiplexed onto one path and selected separately through the combination of the code division and wavelength division multiplexing and demultiplexing.

Two-way CATV system using frequency division multiplexing

Abstract: A two-way CATV system, in which a plurality of communication channels are set simultaneously in an upstream communication line between a plurality of end terminal equipment and a center equipment by using frequency division multiplexing, is disclosed A digital transmultiplexer is arranged at each junction between a trunk line and a branch line for converting a frequency division multiplex signal into a time division multiplex signal Frequency division multiplex signals from the terminal equipment are converted into time division multiplex signals, and then only a time slot corresponding to a frequency slot containing a signal therein is picked up to thereby prevent upstream noises from flowing into the trunk line

Multiplication, division and square root extraction apparatus

Abstract: A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.

Optimal size integer division circuits

Abstract: Division is a fundamental problem for arithmetic and algebraic computation. This paper describes Boolean circuits (of bounded fan-in) for integer division (finding reciprocals) that have size O(M(n)) and depth O(lognlog logn), where M(n) is the size complexity of O(logn) depth integer multiplication circuits. Currently, M(n) is known to be O(nlogn log,n), but any improvement in this bound that preserves circuit depth will be reflected by a similar improvement in the size complexity of our division algorithm. Previously, no one has been able to derive a division circuit with size O(n logcn) for any c, and simultaneous depth less than O(log2n). Our circuits are logspace uniform; that is, they can be constructed by a deterministic Turing machine in space O(log n).Our results match the best known depth bounds for logspace uniform circuits, and are optimal in size.The general method of high order iterative formulas is of independent interest as a way of efficiently using parallel processors to solve algebraic problems. In particular, our algorithm implies that any rational function can be evaluated in these complexity bounds.As an introduction to high order iterative methods we also present a circuit for finding polynomial reciprocals (where the coefficients come from an arbitrary ring, and ring operations are unit cost in the circuit) in size O(PM (n)) and depth O(log n log log n), where PM(n) is the size complexity of optimal depth polynomial multiplication.

Time division multiplex arrangement

Abstract: Modems, data service units (109-111), application modules (108, 112, 114, 115) and other data communication devices (102-106), installed in a common equipment cabinet, are interconnected by way of a time division multiplexed bus (RB, WB, TSA, TYPE). Time slots assigned to the various devices recur at a number of regularly-spaced access periods across each time division multiplex frame. The rate at which the access periods occur and the total number of access periods that make up each frame are chosen in such a way as to accomodate a mix of devices having respective bus access rates wherein there is at least one pair of rates for which neither rate of the pair is a whole number multiple of the other. The process of allocating access periods to the time slots is carried out using a known lemma to identify linear Diophantine equation solutions.

Voltage regulator load division using real and reactive generator output power components to control the exciter

Abstract: The problem for distributing load equally between multiple generators (34) in multi-channel generating systems is resolved using a voltage regulator (60) including a reactive load division loop (84) and real load division loop (86) The voltage regulator (60) controls generator excitation responsive to sensed voltage The reactive load division loop and real load division loop modify the voltage regulator output to divide loading equally between each generator

Fast radix-2 division with quotient-digit prediction

Abstract: An implementation of a radix-2 division unit is presented that uses prediction of the quotient digit. This prediction allows the concurrent computation of the quotient digit and the partial remainder. To achieve a simple quotient-digit selection, resulting in a step time roughly half of that of SRT division (without prediction), a simple estimate of the partial remainder is used, which requires that the divisor be scaled close to unity. This prescaling is simple to implement and increases the execution time by two cycles. We estimate a speed-up of 1.5 with respect to SRT division with redundant remainders.

Relational division: four algorithms and their performance

Abstract: Three known algorithms for relational division, the algebra operator used to express universal quantification (for-all conditions) and an algorithm called hash-division are outlined. By comparing the algorithms analytically and experimentally, it is shown that the algorithm provides performance competitive with or superior to that of techniques used to date, namely techniques using sorting or aggregate functions. Furthermore, the algorithm can eliminate duplicates in the divisor on the fly, ignores duplicates in the dividend, and allows two kinds of partitioning, either of which can be used to resolve hash table overflow or to efficiently implement the algorithm on a multiprocessor system. >

Generic interpolation pipeline processor

Abstract: A generic interpolation pipeline processor for use in a real-time video display system to find the coordinates of any point P(x,y) on a line between P₁(x₁,y₁) and P₂(x₂,y₂) according to the equation comprises an apparatus for performing integer interpolation calculations (200) using a single independent variable to calculate two dependent variables in parallel and further includes apparatus (202, 204, 206) for merging division and multiplication operations so as to increase throughput as compared to a division pipeline followed by a multiply pipeline.

Cascade: hardware for high/variable precision arithmetic

Abstract: The Cascade hardware architecture for high/variable precision arithmetic is described. It uses a radix-16 redundant signed-digit number representation and directly supports single or multiple precision addition, subtraction, multiplication, division, extraction of the square root, and computation of the greatest divisor. It is object-oriented and implements an abstract class of objects, variable precision integers. It provides a complete suite of memory management functions implemented in hardware, including a garbage collector. The Cascade hardware permits free tradeoffs of space versus time. >

Frame for motorcycle

Abstract: PURPOSE:To improve rigidity, by a method wherein, when a head pipe is formed by means of curved parts located to the fronts of division frames on both sides, joint parts surrounding a ring member are integrally welded together in a state that the ring member is engaged between the curved parts. CONSTITUTION:A title frame is formed with division frames 10 and 20 in the shape of a square pipe on both sides which are molded by aluminum casting. Curved parts 11 and 21 approximately in a semiarcuate in cross section are formed in a protruding manner to the tips of the division frames 10 and 20, and the two curved parts 11 and 21 are mated to each other to form a head pipe H. The division frames 10 and 20 are extended rearward toward an oblique downward position, and a down pipe 15 or 25 and a rear pipe 16 or 26 are branched from a part of the division frame. Upper and lower ring members 30 and 32 are engaged with the upper and lower inner parts of curved spaces 13 and 23 of the division frames 10 and 20, and are welded to joint parts between the curved parts 11 and 21, upper and lower notch parts 12a, 12b and 22a, 22b, and the division frames 10 and 20.

Effects of asymmetric division on a stochastic model of the cell division cycle.

Abstract: The stochastic model of cell division formulated by Alt and Tyson is generalized to the case of imprecise binary fission. Closed-form expressions are derived for the generation-time distribution, the birth-size and division-size distributions, the β curve, and the correlation coefficient of generation times of sister cells. The theoretical results are compared to observations of cell division statistics in a culture of fission yeast.

An asynchronous time division network

Abstract: The asynchronous time division network transmits data by way of high rate bearers. The data is divided into fixed length packets. The network comprises a switching matrix having a number of input and output ports arranged in columns. Each data packet is routed from an input port to a defined output port via addressed switching nodes. Each node has a queueing means, and each queueing means of each output column is tested and priority is given to the first queueing means tested which holds more than one packet.

Integer division circuit provided with a overflow detector circuit

Abstract: An integer division circuit performs a division operation on a dividend and a divisor each accomplished with sign information. The circuit includes a first latch circuit for temporarily storing, as sign control data, exclusive-OR operation data of the sign information of the dividend and divisor, an operation unit for forming a division operation on absolute value data of the dividend and divisor to produce a quotient, a correction circuit for correcting a sign of the quotient in response to the sign control data, and an overflow detection circuit for performing an exclusive-OR operation on the corrected-sign of the quotient and the sign control data to produce an overflow detection signal.

Division sheet feeding apparatus and method

Abstract: A division sheet feeding method comprises the steps of laying at least one division sheet, which is fed by a division sheet conveyance device, upon a group of a predetermined number of product sheets each time the predetermined number of the product sheets are stacked one upon another by a sheet stacking device in the course of cutting a product web by a product web cutting device into the product sheets having predetermined sizes, conveying the product sheets by a product sheet conveyance device, and stacking the product sheets by the sheet stacking device. A division sheet web is cut as required to obtain the division sheet, and the division sheet is fed to the division sheet conveyance device.

Simulations with a large number of neurons

Abstract: The authors propose a new algorithm for evolution of neural networks, by division of the network into subnets, in order to reach retrieval of stored correlated patterns. They present a fast code for simulations with a large number of neurons ( approximately 10000). The simulations were carried out on a microcomputer.

Implementation of module combining multiplication, division, and square root

Abstract: The implementation of a module that performs radix-2 multiplication, division, and square root is presented. The module is compact because most of the components are shared by all three operations, the complexity being similar to that of a radix-2 divider. All three operations have the same execution time; one bit of the result is produced per cycle, beginning with the most significant bit. The cycle time is kept small by the use of carry-save addition and result-digit selection based on a low-precision estimate of the partial remainder. The module incorporates on-the-fly conversion and routing of the result. >

Design of on-line division unit

Abstract: A gate array implementation of a radix-2 floating-point online division algorithm is presented. The design requires 111 equivalent gates per bit and has a cycle time of 24 ns. For 8-b exponent and 24-b mantissa, the design requires 2497 equivalent gates and can fit on an LSI Logic LL9320P chip with a utilization factor 78%. >

Time division communication system frame changeover arrangement

Abstract: A frame organized time division multiplex communication system includes a central office and at least one remote terminal. A time division link connected between each remote terminal and the central office carries signals organized in time division multiplex frames. The central office determines the time division multiplex link frame format. Each remote terminal has at least one interface connected to the time division link that multiplexes signals into the time division multiplex frames, demultiplexes signals from the time division multiplex frames and monitors the time division frames from the time division link for in-frame and out-of-frame operation. An interface controller in the remote terminal determines the frame configuration of the interface multiplexing and demultiplexing. The controller identifies interfaces exhibiting out-of-frame operation and automatically switches the identified out-of-frame interfaces to an alternate frame configuration. The remote terminal frame configuration is thereby adjusted to correspond to a change in time division link frame format.

Arithmetic unit for inverse trigonometric function

Abstract: An arithmetic unit carries out sequentially arithmetic pseudo division and reverse-sequentially arithmetic pseudo multiplication according to algolithm based on CORDIC method utilizing constant values 2 k xarctan(2 -k ) so as to calculate value of inverse trigonometric function arctan y/x. A generater sequentially generates constant values 2 k xarctan(2 -k ) from k=m-1 to k=0 where k=0, 1, . . . , m-1. A first register is operable during the pseudo division for storing a first variable and operable during the pseudo multiplication for storing a destined variable. A second register is operable during the pseudo division for storing a second variable. A barrel shifter right-shifts the value of second variable by a given shaft bit count 2k where k=1, 2, . . . , m-2, m-1, m. A first adder-subtracter operates during the psuedo division for selectively adding or subtracting the right-shifted value of second variable to or from the value of first variable to output the result into the first register to thereby update the value of first variable, and operates during the pseudo multiplication for selectively adding or subtracting the constant value of generator to or from the value of destined variable stored in the first register to output the result into the first register to thereby update the value of destined variable. A second adder-subtracter operates during the pseudo division for selectively adding or subtracting the value of first variable to or from the value of second variable to output the result into the second register to thereby update the value of second variable. An m-stage stacker operates to process a sign bit of the second variable in First-In, Last-Out basis for controlling the first and second adder-subtracters to selectively carry out adding or subtracting operation.

Equations in division rings—a survey

Abstract: (1989). Equations in Division Rings—A Survey. The American Mathematical Monthly: Vol. 96, No. 3, pp. 220-232.

A 50 MHz uniformly pipelined 64 b floating-point arithmetic processor

Abstract: A description is given of a uniformly pipelined, 50-MHz, 64-b floating-point arithmetic processor implemented in a 1.5- mu m (drawn) CMOS technology which performs single- and double-precision floating-point operations and integer multiplication as defined by a superminicomputer architecture standard. The chip is composed of an interface section and a five-segment execution core. The core insists of a divider, bypassed in all instruction except division, and four fully pipelined stages that are uniformly utilized in the execution of all instructions. The performance is summarized. First pass silicon has been functionally verified at 50 MHz with a set of over one million vectors. >

Scale for use for measurement of the displacement of an object to be examined, and displacement measuring apparatus

Abstract: A scale, for measuring the displacement of an object to be examined, has a division and a mark for alignment of the division, and a displacement measuring apparatus, for measuring the displacement of a scale, has a device for reading the division of the scale and a detector for detecting the positional error of the division relative to the direction of the displacement.